9FGV0631C DATASHEET
Pin Descriptions
PIN #
PIN NAME
1 vSS_EN_tri
2 X1_25
3 X2
4 VDDXTAL1.8
5 VDDREF1.8
6 vSADR/REF1.8
7 NC
8 GNDDIG
9 SCLK_3.3
10 SDATA_3.3
11 VDDDIG1.8
12 VDDIO
13 vOE0#
14 DIF0
15 DIF0#
16 VDD1.8
17 VDDIO
18 DIF1
19 DIF1#
20 NC
21 vOE1#
22 DIF2
23 DIF2#
24 vOE2#
25 NC
26 VDDA1.8
27 VDDIO
28 DIF3
29 DIF3#
30 vOE3#
31 VDD1.8
32 VDDIO
33 DIF4
34 DIF4#
35 vOE4#
36 DIF5
37 DIF5#
38 vOE5#
39 VDDIO
40 ^CKPWRGD_PD#
41 ePAD
PIN TYPE
DESCRIPTION
LATCHED Latched select input to select spread spectrum amount at initial power up :
IN
1 = -0.5% spread, M = -0.25%, 0 = Spread Off
IN
Crystal input, Nominally 25.00MHz.
OUT Crystal output.
PWR Power supply for XTAL, nominal 1.8V
PWR VDD for REF output. nominal 1.8V.
LATCHED
I/O
Latch to select SMBus Address/1.8V LVCMOS copy of X1/REFIN pin
N/A No Connection.
GND Ground pin for digital circuitry
IN
Clock pin of SMBus circuitry, 3.3V tolerant.
I/O Data pin for SMBus circuitry, 3.3V tolerant.
PWR 1.8V digital power (dirty power)
PWR Power supply for differential outputs
IN
Active low input for enabling DIF pair 0. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
OUT Differential true clock output
OUT Differential Complementary clock output
PWR Power supply, nominal 1.8V
PWR Power supply for differential outputs
OUT Differential true clock output
OUT Differential Complementary clock output
N/A No Connection.
IN
Active low input for enabling DIF pair 1. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
OUT Differential true clock output
OUT Differential Complementary clock output
Active low input for enabling DIF pair 2. This pin has an internal pull-down.
IN
1 =disable outputs, 0 = enable outputs
N/A No Connection.
PWR 1.8V power for the PLL core.
PWR Power supply for differential outputs
OUT Differential true clock output
OUT Differential Complementary clock output
IN
Active low input for enabling DIF pair 3. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
PWR Power supply, nominal 1.8V
PWR Power supply for differential outputs
OUT Differential true clock output
OUT Differential Complementary clock output
IN
Active low input for enabling DIF pair 4. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
OUT Differential true clock output
OUT Differential Complementary clock output
IN
Active low input for enabling DIF pair 5. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
PWR Power supply for differential outputs
Input notifies device to sample latched inputs and start up on first high assertion. Low enters
IN
Power Down Mode, subsequent high assertions exit Power Down Mode. This pin has internal
pull-up resistor.
GND Connect paddle to ground.
JUNE 23, 2017
3
6-OUTPUT VERY LOW-POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR