9FGV0441 View Datasheet(PDF) - Integrated Device Technology
Part Name
Description
Manufacturer
9FGV0441 Datasheet PDF : 16 Pages
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9FGV0441
4-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
SMBus Table: Output Enable Register
Byte 0
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DIF OE3
DIF OE3
DIF OE2
DIF OE1
Control Function
Reserved
Reserved
Reserved
Reserved
Output Enable
Output Enable
Output Enable
Output Enable
Type
RW
RW
RW
RW
0
Low/Low
Low/Low
Low/Low
Low/Low
1
Enabled
Enabled
Enabled
Enabled
Default
1
1
1
1
1
1
1
1
SMBus Table: SS Readback and Vhigh Control Register
Byte 1
Bit 7
Bit 6
Name
SSENRB1
SSENRB1
Control Function
SS Enable Readback Bit1
SS Enable Readback Bit0
Bit 5
SSEN_SWCNTRL
Enable SW control of SS
Bit 4
SSENSW1
SS Enable Software Ctl Bit1
Bit 3
SSENSW0
SS Enable Software Ctl Bit0
Bit 2
Reserved
Bit 1
Bit 0
AMPLITUDE 1
AMPLITUDE 0
Controls Output Amplitude
1. B1[5] must be set to a 1 for these bits to have any effect on the part.
Type
0
1
R 00' for SS_EN_tri = 0, '01' for SS_EN_tri
R
= 'M', '11 for SS_EN_tri = '1'
RW
SS control locked
Values in B1[4:3]
control SS amount.
RW1
RW1
00' = SS Off, '01' = -0.25% SS,
'10' = Reserved, '11'= -0.5% SS
RW
00 = 0.6V
RW
10= 0.8V
01 = 0.7V
11 = 0.9V
Default
Latch
Latch
0
0
0
1
1
0
SMBus Table: DIF Slew Rate Control Register
Byte 2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
SLEWRATESEL DIF3
SLEWRATESEL DIF2
SLEWRATESEL DIF1
SLEWRATESEL DIF0
Control Function
Reserved
Reserved
Reserved
Reserved
Adjust Slew Rate of DIF3
Adjust Slew Rate of DIF2
Adjust Slew Rate of DIF3
Adjust Slew Rate of DIF1
Type
RW
RW
RW
RW
0
2.0V/ns
2.0V/ns
2.0V/ns
2.0V/ns
1
3.0V/ns
3.0V/ns
3.0V/ns
3.0V/ns
Default
1
1
1
1
1
1
1
1
SMBus Table: REF Control Register
Byte 3
Name
Bit 7
Bit 6
REF
Bit 5 REF Power Down Function
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REF OE
Control Function
Slew Rate Control
Wake-on-Lan Enable for REF
REF Output Enable
Reserved
Reserved
Reserved
Reserved
Type
0
1
RW
00 = Slowest
01 = Slow
RW
10 = Fast
11 = Faster
RW
REF does not run in REF runs in Power
Power Down
Down
RW
Low
Enabled
Default
0
1
0
1
1
1
1
1
Byte 4 is reserved and reads back 'hFF'.
IDT® 4-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
10
9FGV0441
JUNE 22, 2017
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