9FGV0241
2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating
Conditions
TA = TCOM or TIND; Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS NOTES
1.8V Supply Voltage
VDD
Supply voltage for core, analog and single-ended
LVCMOS outputs
1.7
1.8
1.9
V
1
Ambient Operating
TCOM
Commercial range
0
25
70
°C
1
Temperature
TIND
Industrial range
-40
25
85
°C
1
Input High Voltage
VIH
Single-ended inputs, except SMBus
0.75 VDD
VDD + 0.3 V
1
Input Mid Voltage
VIM Single-ended tri-level inputs ('_tri' suffix, if present) 0.4 VDD
0.6 VDD
V
1
Input Low Voltage
VIL
Schmitt Trigger Positive
Going Threshold Voltage
VT+
Single-ended inputs, except SMBus
Single-ended inputs, where indicated
-0.3
0.4 VDD
0.25 VDD V
1
0.7 VDD
V
1
Schmitt Trigger Negative
Going Threshold Voltage
VT-
Single-ended inputs, where indicated
0.1 VDD
0.4 VDD
V
1
Hysteresis Voltage
VH
VT+ - VT-
0.1 VDD
0.4 VDD
V
1
Output High Voltage
VIH
Single-ended outputs, except SMBus. IOH = -2mA VDD-0.45
V
1
Output Low Voltage
VIL
Single-ended outputs, except SMBus. IOL = -2mA
0.45
V
1
IIN
Single-ended inputs, VIN = GND, VIN = VDD
-5
5
uA
1
Input Current
Single-ended inputs
IINP
VIN = 0 V; Inputs with internal pull-up resistors
-200
VIN = VDD; Inputs with internal pull-down resistors
200
uA
1
Input Frequency
Fin
XTAL, or X1 input
23
25
27
MHz
1
Pin Inductance
Lpin
7
nH
1
Capacitance
CIN
Logic Inputs, except DIF_IN
1.5
COUT
Output pin capacitance
5
pF
1
6
pF
1
Clk Stabilization
TSTAB
From VDD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
0.4
1.8
ms
1,2
SS Modulation Frequency
fMOD
Allowable Frequency
(Triangular Modulation)
31
31.6
32
kHz
1
OE# Latency
tLATOE#
DIF start after OE# assertion
DIF stop after OE# deassertion
2
3
4
clocks 1,3
Tdrive_PD#
tDRVPD
DIF output enable after
PD# de-assertion
4
300
us
1,3
Tfall
tF
Fall time of single-ended control inputs
5
ns
1,2
Trise
tR
Rise time of single-ended control inputs
5
ns
1,2
SMBus Input Low Voltage VILSMB
VDDSMB = 3.3V, see note 4 for VDDSMB < 3.3V
0.8
V
1,4
SMBus Input High Voltage VIHSMB
VDDSMB = 3.3V, see note 5 for VDDSMB < 3.3V
2.1
3.6
V
1,5
SMBus Output Low Voltage VOLSMB
@ IPULLUP
0.4
V
1
SMBus Sink Current
IPULLUP
@ VOL
4
mA
1
Nominal Bus Voltage
VDDSMB
1.7
3.6
V
1
SCLK/SDATA Rise Time
tRSMB
(Max VIL - 0.15) to (Min VIH + 0.15)
1000
ns
1
SCLK/SDATA Fall Time
SMBus Operating
Frequency
tFSMB
fMAXSMB
(Min VIH + 0.15) to (Max VIL - 0.15)
Maximum SMBus operating frequency
300
ns
1
400
kHz
1
1 Guaranteed by design and characterization, not 100% tested in production.
2 Control input must be monotonic from 20% to 80% of input swing.
3 Time from deassertion until outputs are >200 mV
4 For VDDSMB < 3.3V, VILSMB <= 0.35VDDSMB
5 For VDDSMB < 3.3V, VIHSMB >= 0.65VDDSMB
IDT® 2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
6
9FGV0241
JUNE 22, 2017