9FGV0231 View Datasheet(PDF) - Integrated Device Technology
Part Name
Description
Manufacturer
9FGV0231 Datasheet PDF : 16 Pages
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9FGV0231
2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
Pin Descriptions
Pin#
1
2
3
Pin Name
X1_25
X2
VDDXTAL1.8
4 vSADR/REF1.8
5 GNDREF
6 GNDDIG
7 VDDDIG1.8
8 SCLK_3.3
9 SDATA_3.3
10 GND
11 VDD1.8
12 vOE0#
13 DIF0
14 DIF0#
15 GNDA
16 VDDA1.8
17 DIF1
18 DIF1#
19 vOE1#
20 VDD1.8
21 GND
22 ^CKPWRGD_PD#
23 vSS_EN_tri
24 GNDXTAL
Type Pin Description
IN
Crystal input, Nominally 25.00MHz.
OUT
Crystal output.
PWR Power supply for XTAL, nominal 1.8V
LATCHED
I/O
Latch to select SMBus Address/1.8V LVCMOS copy of X1 pin.
GND Ground pin for the REF outputs.
GND Ground pin for digital circuitry
PWR 1.8V digital power (dirty power)
IN
Clock pin of SMBus circuitry, 3.3V tolerant.
I/O
Data pin for SMBus circuitry, 3.3V tolerant.
GND Ground pin.
PWR Power supply, nominal 1.8V
IN
Active low input for enabling DIF pair 0. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
OUT
Differential true clock output
OUT
Differential Complementary clock output
GND Ground pin for the PLL core.
PWR 1.8V power for the PLL core.
OUT
Differential true clock output
OUT
Differential Complementary clock output
IN
Active low input for enabling DIF pair 1. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
PWR Power supply, nominal 1.8V
GND Ground pin.
Input notifies device to sample latched inputs and start up on first high assertion.
IN
Low enters Power Down Mode, subsequent high assertions exit Power Down
Mode. This pin has internal pull-up resistor.
LATCHED IN
Latched select input to select spread spectrum amount at initial power up :
1 = -0.5% spread, M = -0.25%, 0 = Spread Off
GND GND for XTAL
IDT® 2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
3
9FGV0231
JUNE 22, 2017
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