M24128, M24C64, M24C32
DC and AC parameters
Table 17. AC characteristics (VCC = 2.5V to 5.5V, device grades 6 and 3)
Test conditions specified in Table 11 and Table 8
Symbol Alt.
Parameter
Min. Max. Unit
fC
fSCL Clock Frequency
400 kHz
tCHCL tHIGH Clock Pulse Width High
600
ns
tCLCH
tDL1DL2(1)
tLOW
tF
Clock Pulse Width Low
SDA Fall Time
1300
20
ns
300 ns
tDXCX tSU:DAT Data In Set Up Time
100
ns
tCLDX tHD:DAT Data In Hold Time
0
ns
tCLQX
tCLQV(2)
tCHDX(3)
tDH
tAA
tSU:STA
Data Out Hold Time
Clock Low to Next Data Valid (Access Time)
Start Condition Set Up Time
200
ns
200 900 ns
600
ns
tDLCL tHD:STA Start Condition Hold Time
600
ns
tCHDH tSU:STO Stop Condition Set Up Time
600
ns
tDHDL
tBUF Time between Stop Condition and Next Start Condition 1300
ns
tW
tWR Write Time
5 ms
1. Sampled only, not 100% tested.
2. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the
falling or rising edge of SDA.
3. For a reSTART condition, or following a Write cycle.
Table 18. AC characteristics (VCC = 1.8V to 5.5V or VCC = 1.7V to 5.5V)
Test conditions specified in Table 11 and Table 9 or Table 10
Symbol Alt.
Parameter
Min. Max. Unit
fC
fSCL Clock Frequency
400 kHz
tCHCL tHIGH Clock Pulse Width High
600
ns
tCLCH tLOW Clock Pulse Width Low
tDL1DL2(1) tF SDA Fall Time
1300
ns
20 300 ns
tDXCX tSU:DAT Data In Set Up Time
100
ns
tCLDX tHD:DAT Data In Hold Time
0
ns
tCLQX
tCLQV(2)
tCHDX(3)
tDH Data Out Hold Time
tAA Clock Low to Next Data Valid (Access Time)
tSU:STA Start Condition Set Up Time
200
ns
200 900 ns
600
ns
tDLCL tHD:STA Start Condition Hold Time
600
ns
tCHDH tSU:STO Stop Condition Set Up Time
600
ns
tDHDL tBUF Time between Stop Condition and Next Start Condition 1300
ns
tW
tWR Write Time
10 ms
1. Sampled only, not 100% tested.
2. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the
falling or rising edge of SDA.
3. For a reSTART condition, or following a Write cycle.
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