74LS192 View Datasheet(PDF) - ON Semiconductor

Part Name

Description

Manufacturer

74LS192

PRESETTABLE BCD/DECADE UP/DOWN COUNTER PRESETTABLE 4-BIT BINARY UP/DOWN COUNTER

ON Semiconductor 

SN74LS192

AC CHARACTERISTICS (TA = 25°C)

Limits

Symbol

Parameter

Min Typ Max Unit

Test Conditions

fMAX

Maximum Clock Frequency

25

32

MHz

tPLH

CPU Input to

tPHL

TCU Output

17

18

26

24

ns

tPLH

tPHL

tPLH

tPHL

CPD Input to

TCD Output

Clock to Q

16

15

24

24

ns

27

30

38

47

ns

VCC = 5.0 V

CL = 15 pF

tPLH

tPHL

PL to Q

24

25

40

40

ns

tPHL

MR Input to Any Output

AC SETUP REQUIREMENTS (TA = 25°C)

23

35

ns

Limits

Symbol

Parameter

Min Typ Max Unit

Test Conditions

tW

Any Pulse Width

20

ns

ts

Data Setup Time

20

ns

VCC = 5.0 V

th

Data Hold Time

5.0

ns

trec

Recovery Time

DEFINITIONS OF TERMS

40

ns

SETUP TIME (ts) is defined as the minimum time required for

the correct logic level to be present at the logic input prior to

the PL transition from LOW-to-HIGH in order to be

recognized and transferred to the outputs.

HOLD TIME (th) is defined as the minimum time following the

PL transition from LOW-to-HIGH that the logic level must be

maintained at the input in order to ensure continued

recognition. A negative HOLD TIME indicates that the

correct logic level may be released prior to the PL transition

from LOW-to-HIGH and still be recognized.

RECOVERY TIME (trec) is defined as the minimum time

required between the end of the reset pulse and the clock

transition from LOW-to-HIGH in order to recognize and

transfer HIGH data to the Q outputs.

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