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6259 Просмотр технического описания (PDF) - Allegro MicroSystems

Номер в каталогеКомпоненты Описаниепроизводитель
6259 8-BIT ADDRESSABLE DMOS POWER DRIVER Allegro
Allegro MicroSystems Allegro
6259 Datasheet PDF : 10 Pages
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6259
8-BIT ADDRESSABLE
DMOS POWER DRIVER
TERMINAL DESCRIPTIONS
Terminal No. Terminal Name
Function
1
POWER GROUND Reference terminal for output voltage measurements (OUT0-3).
2
LOGIC SUPPLY (VDD) The logic supply voltage (typically 5 V).
3
S0
Binary-coded output-select input, least-significant bit.
4
OUT0
Current-sinking, open-drain DMOS output, address 000.
5
OUT1
Current-sinking, open-drain DMOS output, address 001.
6
OUT2
Current-sinking, open-drain DMOS output, address 010.
7
OUT3
Current-sinking, open-drain DMOS output, address 011.
8
S1
Binary-coded output-select input.
9
LOGIC GROUND Reference terminal for input voltage measurements.
10
POWER GROUND Reference terminal for output voltage measurements (OUT0-3).
11
POWER GROUND Reference terminal for output voltage measurements (OUT4-7).
12
S2
Binary-coded output-select input, most-significant bit.
13
ENABLE
Mode control input; see Function Table.
14
OUT4
Current-sinking, open-drain DMOS output, address 100.
15
OUT5
Current-sinking, open-drain DMOS output, address 101.
16
OUT6
Current-sinking, open-drain DMOS output, address 110.
17
OUT7
Current-sinking, open-drain DMOS output, address 111.
18
DATA
CMOS data input to the addressed output latch. When enabled, the
addressed output inverts the data input (DATA = HIGH, OUTPUT = LOW).
19
CLEAR
Mode control input; see Function Table.
20
POWER GROUND Reference terminal for output voltage measurements (OUT4-7).
NOTE — Grounds (terminals 1, 9, 10, 11, and 20) must be connected externally to a single point.
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