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FAN100(2010_01) View Datasheet(PDF) - Fairchild Semiconductor

Part Name
Description
Manufacturer
FAN100 Datasheet PDF : 21 Pages
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AN-6067
APPLICATION NOTE
Startup Circuitry
When the power is activated, the input voltage charges the
hold-up capacitor (C1) via the startup resistors, as shown in
Figure 20. As the voltage (VDD) reaches the startup voltage
threshold (VDD-ON), the PSR controller activates and drives
the entire power supply.
The maximum power dissipation of RIN is:
( ) PRIN ,MAX
=
Vdc,max VDD
RIN
2
V2
dc,max
RIN
(3)
where Vdc,max is the maximum rectified input voltage.
VDD
PSR
Controller
GND
Vdc
R IN
TD_ON
D1
C1
Figure 20. Single-Step Circuit Connected to the
PSR Controller
The power-on delay is determined as follows:
TD _ON = −RIN C1 ln⎜⎜⎝⎛1 Vac
VDDON
2 I DDST
RIN
⎟⎟⎠⎞
(2)
where IDD-ST is the startup current of the PSR controller.
Due to the low startup current, a large RIN value, such as
1.5MΩ can be used. With a hold-up capacitor of 4.7µF, the
power-on delay TD_ON is less than 3s for a 90VAC input.
If a shorter startup time is required, a two-step startup
circuit, as shown in Figure 21, is recommended. In this
circuit, a smaller C1 capacitor can be used to decrease
startup time without a need for a smaller startup resistor
(RIN) and increase the power dissipation on the RIN resistor.
The energy supporting the PSR controller after startup is
mainly from a larger capacitor C2.
VDD
PSR
Controller
Vdc
R IN
TD_ON
C1
C2
Take a wide-ranging input (90VAC~264VAC) as an example,
Vdc =100V~380V:
PRIN ,MAX
= 3802
1.5 ×106
96mW
(4)
Built-in Slope Compensation
The sensed voltage across the current sense resistor is used
for peak-current-mode control and cycle-by-cycle current
limiting. Within every switching cycle, the PSR controller
produces a positively sloped, synchronized ramp signal. The
built-in slope compensation function improves power supply
stability and prevents peak-current-mode control from
causing sub-harmonic oscillations.
Leading Edge Blanking (LEB)
Each time the MOSFET is powered on, a spike, induced by
the diode reverse recovery and by the output capacitances of
the MOSFET and diode, appears on the sensed signal. To
avoid premature termination of the MOSEFT, a leading-
edge blanking time is introduced in the PSR controller.
During the blanking period, the current-limit comparator is
disabled and unable to switch off the gate driver.
Under-Voltage Lockout (UVLO)
The power-on and off thresholds of the PSR controller are
fixed at 16V/5V. During startup, the hold-up capacitor must
be charged to 16V through the startup resistor to enable PSR
controller. The hold-up capacitor continues to supply VDD
until power can be delivered from the auxiliary winding of
the main transformer (VDD must not drop below 5V during
this startup process). This UVLO hysteresis window ensures
that the hold-up capacitor can adequately supply VDD during
startup.
VDD Over-Voltage Protection (OVP)
VDD over-voltage protection prevents damage due to over-
voltage conditions. When VDD exceeds 28V due to abnormal
conditions, PWM output is turned off. Over-voltage
conditions are usually caused by open feedback loops.
GND
Over-Temperature Protection (OTP)
Figure 21. Two Steps of Providing Power to the
PSR Controller
© 2008 Fairchild Semiconductor Corporation
Rev. 1.0.1 • 1/26/10
The PSR controller has a built-in temperature sensing circuit
to shut down the PWM output if the junction temperature
exceeds 145°C. When the PWM output shuts down, the VDD
voltage gradually drops to the UVLO voltage. Some of the
internal circuits shut down and VDD gradually starts
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