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M12L64164A-7TIG View Datasheet(PDF) - [Elite Semiconductor Memory Technology Inc.

Part Name
Description
Manufacturer
M12L64164A-7TIG
ESMT
[Elite Semiconductor Memory Technology Inc. ESMT
M12L64164A-7TIG Datasheet PDF : 45 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
ESMT
M12L64164A
Operation Temperature Condition -40°C~85°C
AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V TA = -40 to 85 °C )
PARAMETER
Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall-time
Output timing measurement reference level
Output load condition
VALUE
2.4/0.4
1.4
tr/tf = 1/1
1.4
See Fig. 2
UNIT
V
V
ns
V
Output
870
3.3V
1200
VOH (DC) =2.4V , IOH = -2 mA
VOL (DC) =0.4V , IOL = 2 mA
50pF
Output
Z0 =50
Vtt = 1.4V
50
50pF
(Fig. 1) DC Output Load Circuit
(Fig. 2) AC Output Load Circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
PARAMETER
SYMBOL
Row active to row active delay
tRRD(min)
RAS to CAS delay
tRCD(min)
Row precharge time
tRP(min)
Row active time
tRAS(min)
tRAS(max)
Row cycle time
@ Operating
@ Auto refresh
tRC(min)
tRFC(min)
Last data in to col. address delay
tCDL(min)
Last data in to row precharge
tRDL(min)
Last data in to burst stop
tBDL(min)
Col. address to col. address delay
tCCD(min)
Number of valid
Output data
CAS latency = 3
CAS latency = 2
VERSION
-5
-6
-7
10
12
14
15
18
20
15
18
20
38
40
42
100
53
58
63
55
60
70
1
2
1
1
2
1
UNIT
ns
ns
ns
ns
us
ns
ns
CLK
CLK
CLK
CLK
ea
NOTE
1
1
1
1
1
1,5
2
2
2
3
4
Note : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer.
2. Minimum delay is required to complete with.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. A new command may be given tRFC after self refresh exit.
Elite Semiconductor Memory Technology Inc.
Publication Date: Dec. 2007
Revision: 1.2
6/45
 

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