Data Sheet
AD9694
INPUT
ADR130
1 NC NC 6
2 GND SET 5
3 VIN VOUT 4
0.1µF
INTERNAL
VREF
GENERATOR
VREF
0.1µF
VREF PIN AND
FULL-SCALE
VOLTAGE
CONTROL
FULL-SCALE
VOLTAGE
ADJUST
Figure 60. External Reference Using the ADR130
Register 0x18A6 enables the user to either use this internal 0.5 V
reference, or to provide an external 0.5 V reference. When using
an external voltage reference, provide a 0.5 V reference. The
full-scale adjustment is made using the SPI, irrespective of the
reference voltage. For more information on adjusting the full-
scale level of the AD9694, refer to the Memory Map section.
The SPI writes required to use the external voltage reference, in
order, are as follows:
1. Set Register 0x18E3 to 0x00 to turn off VCM export.
2. Set Register 0x18E6 to 0x00 to turn off temperature diode
export.
3. Set Register 0x18A6 to 0x01 to turn on the external voltage
reference.
The use of an external reference may be necessary, in some
applications, to enhance the gain accuracy of the ADC or to
improve thermal drift characteristics.
The external reference has to be a stable 0.5 V reference. The
ADR130 is a good option for providing the 0.5 V reference.
Figure 60 shows how the ADR130 can be used to provide the
external 0.5 V reference to the AD9694. The grayed out areas
show unused blocks within the AD9694 while using the
ADR130 to provide the external reference.
DC OFFSET CALIBRATION
The AD9694 contains a digital filter to remove the average dc
offset from the output of the ADC. For ac-coupled applications,
this filter can be enabled by writing 0x86 to Register 0x0701.
The filter computes the average dc signal and it is digitally
subtracted from the ADC output. As a result, the dc offset is
improved to better than 70 dBFS at the output. Because the
filter does not distinguish between the source of dc signals, this
feature can be used when the signal content at dc is not of
interest. The filter corrects dc up to 512 codes and saturates
beyond that.
CLOCK INPUT CONSIDERATIONS
For optimum performance, drive the AD9694 sample clock
inputs (CLK+ and CLK−) with a differential signal. This signal
is typically ac-coupled to the CLK+ and CLK− pins via a
transformer or clock drivers. These pins are biased internally
and require no additional biasing.
Figure 61 shows a preferred method for clocking the AD9694. The
low jitter clock source is converted from a single-ended signal to
a differential signal using an RF transformer.
0.1µF
CLOCK
INPUT
50Ω
1:1Z
100Ω
CLK+
ADC
CLK–
0.1µF
Figure 61. Transformer-Coupled Differential Clock
Another option is to ac couple a differential CML or LVDS
signal to the sample clock input pins, as shown in Figure 62 and
Figure 63.
3.3V
71Ω
10pF
33Ω
Z0 = 50Ω
Z0 = 50Ω
33Ω
0.1µF
0.1µF
CLK+
ADC
CLK–
Figure 62. Differential CML Sample Clock
CLOCK INPUT
CLOCK INPUT
0.1µF
CLK+
0.1µF
LVDS
DRIVER
CLK–
50Ω1 50Ω1
0.1µF
CLK+
100Ω ADC
CLK–
0.1µF
150Ω RESISTORS ARE OPTIONAL.
Figure 63. Differential LVDS Sample Clock
Clock Duty Cycle Considerations
Typical high speed ADCs use both clock edges to generate a variety
of internal timing signals. The AD9694 contains an internal clock
divider and a duty cycle stabilizer (DCS). In applications where the
clock duty cycle cannot be guaranteed to be 50%, a higher multiple
frequency clock along with the usage of the clock divider is recom-
mended. When it is not possible to provide a higher frequency
clock, it is recommended to turn on the DCS using Register 0x011C.
The output of the divider offers a 50% duty cycle, high slew rate
(fast edge) clock signal to the internal ADC. See the Memory
Map section for more details on using this feature.
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