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74HCT107-Q100 View Datasheet(PDF) - NXP Semiconductors.

Part Name
Description
Manufacturer
74HCT107-Q100
NXP
NXP Semiconductors. NXP
74HCT107-Q100 Datasheet PDF : 17 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
NXP Semiconductors
74HC107-Q100; 74HCT107-Q100
Dual JK flip-flop with reset; negative-edge trigger
Table 7. Dynamic characteristics …continued
GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 7
Symbol Parameter Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max
Min
Max
th
hold time
nJ, nK to nCP; see Figure 5
VCC = 2.0 V
3 6 -
3
-
3
- ns
VCC = 4.5 V
3 2 -
3
-
3
- ns
VCC = 6.0 V
3 2 -
3
-
3
- ns
fmax
maximum
nCP input; see Figure 5
frequency
VCC = 2.0 V
6 23 - 4.8
-
4.0
- MHz
VCC = 4.5 V
30 70 -
24
-
20
- MHz
VCC = 5.0 V; CL = 15 pF
- 78 -
-
-
-
- MHz
VCC = 6.0 V
35 85 -
28
-
24
- MHz
CPD
power
per flip-flop;
dissipation VI = GND to VCC
capacitance
[3] - 30 -
-
-
-
- pF
74HCT107-Q100
tpd
propagation nCP to nQ; see Figure 5
[1]
delay
VCC = 4.5 V
- 19 36
-
45
-
54 ns
VCC = 5.0 V; CL = 15 pF
- 16 -
-
-
-
- ns
nCP to nQ; see Figure 5
VCC = 4.5 V
VCC = 5.0 V; CL = 15 pF
nR to nQ, nQ; see Figure 6
- 21 36
-
45
-
- 18 -
-
-
-
54 ns
- ns
VCC = 4.5 V
- 20 38
-
48
-
57 ns
VCC = 5.0 V; CL = 15 pF
- 17 -
-
-
-
- ns
tt
transition time nQ, nQ; see Figure 5
[2]
VCC = 4.5 V
- 7 15
-
19
-
22 ns
tW
pulse width nCP input, HIGH or LOW;
see Figure 5
VCC = 4.5 V
nR input, HIGH or LOW;
see Figure 6
16 9 -
20
-
24
- ns
VCC = 4.5 V
20 11 -
25
-
30
- ns
trec
recovery time nR to nCP; see Figure 6
VCC = 4.5 V
14 8 -
18
-
21
- ns
tsu
set-up time nJ, nK to nCP; see Figure 5
VCC = 4.5 V
20 7 -
25
-
30
- ns
th
hold time
nJ, nK to nCP; see Figure 5
VCC = 4.5 V
5 2 -
5
-
5
- ns
74HC_HCT107_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 18 November 2013
© NXP B.V. 2013. All rights reserved.
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