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PI74ALVC162836V View Datasheet(PDF) - Pericom Semiconductor

Part Name
Description
Manufacturer
PI74ALVC162836V
Pericom-Semiconductor
Pericom Semiconductor Pericom-Semiconductor
PI74ALVC162836V Datasheet PDF : 5 Pages
1 2 3 4 5
PI74ALVC162836
1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122
20-Bit Universal Bus Driver
with 3-State Outputs
Product Features
• PI74ALVC162836 is designed for low voltage operation,
VCC = 2.3V to 3.6V
• Supports PC100 Registered DIMM
• Typical VOLP (Output Ground Bounce)
< 0.8V at VCC = 3.3V, TA = 25°C
• Typical VOHV (Output VOH Undershoot)
< 2.0V at VCC = 3.3V, TA = 25°C
• Outputs have equivalent 26series resistors
• Industrial operation at –40°C to +85°C
• Packages available:
– 56-pin 240 mil wide plastic TSSOP (A)
– 56-pin 173 mil wide plastic TVSOP (K)
– 56-pin 300 mil wide plastic SSOP (V)
Product Description
Pericom Semiconductor’s PI74ALVC series of logic circuits are
produced in the Company’s advanced 0.5 micron CMOS technology,
achieving industry leading speed.
The 20-bit PI74ALVC162836 universal bus driver is designed
for 2.3V to 3.6V Vcc operation.
Data flow from A to Y is controlled by the Output Enable (OE) input.
The device operates in the transparent mode when the latch-enable
(LE) input is LOW. When LE is HIGH, the A data is latched if the clock
(CLK) input is held at a high or low logic level. If LE is HIGH, the A
data is stored in the latch/flip-flop on the low-to-high transition of
CLK. When OE is HIGH , the outputs are in the high-impedance state,
but all the inputs are enabled and data is capable of being stored in
the register.
To ensure the high-impedance state during power up or power down,
OE should be tied to Vcc through a pullup resistor; the minimum
value of the resistor is determined by the current-sinking capability
of the driver.
Logic Block Diagram
1
OE
CLK 56
LE 29
A1 55
1D
C1
CLK
2
Y1
TO 19 OTHER CHANNELS
1
PS8204 07/30/98
 

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