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HI-8581CJIF View Datasheet(PDF) - Holt Integrated Circuits

Part NameHI-8581CJIF Holt
Holt Integrated Circuits Holt
DescriptionARINC 429 Transmitter with Line Driver and Dual Receivers
HI-8581CJIF Datasheet PDF : 15 Pages
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HI-8581, HI-8589
FUNCTIONAL DESCRIPTION
CONTROL WORD REGISTER
Both the HI-8581and HI-8589 contain 10 data flip flops whose
D inputs are connected to the data bus and clocks connected to
CWSTR. Each flip flop provides options to the user as follows:
DATA
BUS FUNCTION CONTROL
PIN
DESCRIPTION
BDO5
If enabled, the transmitter’s digital
SELF TEST 0 = ENABLE outputs are internally connected
to the receiver logic inputs
RECEIVER 1
BDO6 DECODER 1 = ENABLE
If enabled, ARINC bits 9 and,
10 must match the next two
control word bits
BDO7
-
If Receiver 1 Decoder is
-
enabled, the ARINC bit 9
must match this bit
BDO8
-
If Receiver 1 Decoder is
-
enabled, the ARINC bit 10
must match this bit
RECEIVER 2
BDO9 DECODER 1 = ENABLE
If enabled, ARINC bits 9 and
10 must match the next two
Control word bits
BD10
-
If Receiver 2 Decoder is
-
enabled, then ARINC bit 9
must match this bit
BD11
-
If Receiver 2 Decoder is
-
enabled, then ARINC bit 10
must match this bit
BD12
INVERT
XMTR
PARITY
Logic 0 enables normal odd parity
1 = ENABLE and Logic 1 enables even parity
output in transmitter 32nd bit
BD13 XMTR DATA
CLK SELECT
0 = ÷10
1 = ÷80
CLK is divided either by 10 or
80 to obtain XMTR data clock
BD14 RCVR DTA
CLK SELECT
0 = ÷10
1 = ÷80
CLK is divided either by 10 or
80 to obtain RCVR data clock
ARINC 429 DATA FORMAT
The following table shows the bit positions in exchanging data with
the receiver or the transmitter. ARINC bit 1 is the first bit
transmitted or received.
BYTE 1
DATA BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD
BUS 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
ARINC 13 12 11 10 9 31 30 32 1 2 3 4 5 6 7 8
BIT
BYTE 2
DATA BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD
BUS 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
ARINC 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14
BIT
THE RECEIVERS
ARINC BUS INTERFACE
Figure 1 shows the input circuit for each receiver. The ARINC 429
specification requires the following detection levels:
STATE
ONE
NULL
ZERO
DIFFERENTIAL VOLTAGE
+6.5 Volts to +13 Volts
+2.5 Volts to -2.5 Volts
-6.5 Volts to -13 Volts
The HI-8581 and HI-8589 guarantee recognition of these levels with
a common mode Voltage with respect to GND less than ±4V for the
worst case condition (4.75V supply and 13V signal level).
The tolerances in the design guarantee detection of the above
levels, so the actual acceptance ranges are slightly larger. If the
ARINC signal is out of the actual acceptance ranges, including the
nulls, the chip rejects the data.
429DI1 (A)
OR
429DI2 (A)
429DI1 (B)
OR
429DI2 (B)
vcc
GND
vcc
DIFFERENTIAL
AMPLIFIERS
COMPARATORS
GND
FIGURE 1. ARINC RECEIVER INPUT
HOLT INTEGRATED CIRCUITS
3
ONES
NULL
ZEROES
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