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EM636165TS-7I View Datasheet(PDF) - Etron Technology

Part NameEM636165TS-7I Etron
Etron Technology Etron
Description1Mega x 16 Synchronous DRAM (SDRAM)


EM636165TS-7I Datasheet PDF : 73 Pages
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EtronTech
1M x 16 SDRAM EM636165-XXI
Figure 15.1. Interleaved Column Write Cycle (Burst Length=4, CAS# Latency=1)
CLK
CKE
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCK1
CS#
RAS#
CAS#
WE #
A11
A10
RAx
RBw
A0~A9
DQM
DQ Hi-Z
RAx CAx RBw
tRCD
CBw
CBx
CBy
CAy
CBz
tRP
tWR tRP
tRRD
DAx0 DAx1 DAx2 DAx3 DBw0 DBw1 DBx0 DBx1 DBy0 DBy1 DAy0 DAy1
DBz0 DBz1 DBz2 DBz3
Activate
Command
Bank A
Activate
Command
Bank B
W rite
Command
Bank A
W rite
W rite
Command Command
Bank B
Bank B
W rite
W rite
Command Command
Bank B
Bank A
W rite
Command
Bank B
Precharge
Command
Bank A
Precharge
Command
Bank B
Preliminary
51
Rev. 1.1 Apr. 2005
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Overview
The EM636165 SDRAM is a high-speed CMOS synchronous DRAM containing 16 Mbits. It is internally configured as a dual 512K word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 512K x 16 bit banks is organized as 2048 rows by 256 columns by 16 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command.
The EM636165 provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with a burst termination option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. By having a programmable mode register, the system can choose the most suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidth and particularly well suited to high performance PC applications

Features
· Fast access time: 5/5.5/6.5/7.5 ns
· Fast clock rate: 166/143/125/100 MHz
· Self refresh mode: standard and low power
· Internal pipelined architecture
· 512K word x 16-bit x 2-bank
· Programmable Mode registers
   - CAS# Latency: 1, 2, or 3
   - Burst Length: 1, 2, 4, 8, or full page
   - Burst Type: interleaved or linear burst
   - Burst stop function
· Individual byte controlled by LDQM and UDQM
· Auto Refresh and Self Refresh
· 4096 refresh cycles/64ms
· CKE power down mode
· Single +3.3V±0.3V power supply
· Interface: LVTTL
· 50-pin 400 mil plastic TSOP II package
· Lead Free Package available

 

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