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EM636165TS-7I View Datasheet(PDF) - Etron Technology

Part NameEM636165TS-7I Etron
Etron Technology Etron
Description1Mega x 16 Synchronous DRAM (SDRAM)


EM636165TS-7I Datasheet PDF : 73 Pages
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EtronTech
EM636165-XXI
1Mega x 16 Synchronous DRAM (SDRAM)
Preliminary (Rev. 1.1, 04/2005)
Features
Fast access time: 5/5.5/6.5/7.5 ns
Fast clock rate: 166/143/125/100 MHz
Self refresh mode: standard and low power
Internal pipelined architecture
512K word x 16-bit x 2-bank
Programmable Mode registers
- CAS# Latency: 1, 2, or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: interleaved or linear burst
- Burst stop function
Individual byte controlled by LDQM and UDQM
Auto Refresh and Self Refresh
4096 refresh cycles/64ms
CKE power down mode
Single +3.3V±0.3V power supply
Interface: LVTTL
50-pin 400 mil plastic TSOP II package
Lead Free Package available
Key Specifications
tCK3
tRAS
tAC3
tRC
EM636165
Clock Cycle time(min.)
Row Active time(max.)
Access time from CLK(max.)
Row Cycle time(min.)
-6I/7I/8I/10I
6/7/8/10ns
36/42/48/60 ns
5/5.5/6.5/7.5 ns
54/63/72/90 ns
Pin Assignment (Top View)
VDD
1
DQ0
2
DQ1
3
VSSQ
4
DQ2
5
DQ3
6
VDDQ
7
DQ4
8
DQ5
9
VSSQ
10
DQ6
11
DQ7
12
VDDQ
13
LDQM
14
WE# 15
CAS#
16
RAS#
17
CS#
18
A11
19
A10
20
A0
21
A1
22
A2
23
A3
24
VDD
25
50
Vss
49
DQ15
48
DQ14
47
VSSQ
46
DQ13
45
DQ12
44
VDDQ
43
DQ11
42
DQ10
41
VSSQ
40
DQ9
39
DQ8
38
VDDQ
37
NC
36
UDQM
35
CLK
34
CKE
33
NC
32
A9
31
A8
30
A7
29
A6
28
A5
27
A4
26
Vss
Ordering Information
Industrial Operating temperature: -40~85°C
Part Number
Frequency
EM636165TS-6I/6IG
166MHz
EM636165TS-7I/7IG
143MHz
EM636165TS-8I/8IG
125MHz
EM636165TS-10I/10IG
100MHz
G : indicates Lead Free Package
Package
TSOP II
TSOP II
TSOP II
TSOP II
Overview
The EM636165 SDRAM is a high-speed CMOS synchronous DRAM containing 16 Mbits. It is internally configured
as a dual 512K word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the
clock signal, CLK). Each of the 512K x 16 bit banks is organized as 2048 rows by 256 columns by 16 bits. Read and
write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed
number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command
which is then followed by a Read or Write command.
The EM636165 provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with a burst
termination option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at
the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. By having a
programmable mode register, the system can choose the most suitable modes to maximize its performance. These
Etron Technology, Inc.
No. 6, Technology Road V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C
TEL: (886)-3-5782345
FAX: (886)-3-5778671
Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice.
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Overview
The EM636165 SDRAM is a high-speed CMOS synchronous DRAM containing 16 Mbits. It is internally configured as a dual 512K word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 512K x 16 bit banks is organized as 2048 rows by 256 columns by 16 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command.
The EM636165 provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with a burst termination option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. By having a programmable mode register, the system can choose the most suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidth and particularly well suited to high performance PC applications

Features
· Fast access time: 5/5.5/6.5/7.5 ns
· Fast clock rate: 166/143/125/100 MHz
· Self refresh mode: standard and low power
· Internal pipelined architecture
· 512K word x 16-bit x 2-bank
· Programmable Mode registers
   - CAS# Latency: 1, 2, or 3
   - Burst Length: 1, 2, 4, 8, or full page
   - Burst Type: interleaved or linear burst
   - Burst stop function
· Individual byte controlled by LDQM and UDQM
· Auto Refresh and Self Refresh
· 4096 refresh cycles/64ms
· CKE power down mode
· Single +3.3V±0.3V power supply
· Interface: LVTTL
· 50-pin 400 mil plastic TSOP II package
· Lead Free Package available

 

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