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EM636165TS-7I View Datasheet(PDF) - Etron Technology

Part NameEM636165TS-7I Etron
Etron Technology Etron
Description1Mega x 16 Synchronous DRAM (SDRAM)


EM636165TS-7I Datasheet PDF : 73 Pages
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EtronTech
1M x 16 SDRAM EM636165-XXI
Electrical Characteristics and Recommended A.C. Operating Conditions
(VDD = 3.3V±0.3V, Ta = -40~85°C) (Note: 5, 6, 7, 8)
Symbol
A.C. Parameter
TRC Row cycle time
(same bank)
tRCD RAS# to CAS# delay
(same bank)
TRP Precharge to refresh/row activate
command (same bank)
tRRD Row activate to row activate delay
(different banks)
tRAS Row activate to precharge time
(same bank)
tWR Write recovery time
TCK1
TCK2
TCK3
TCH
TCL
TAC1
tAC2
tAC3
tCCD
tOH
tLZ
tHZ
tIS
tIH
tPDE
tREF
CL* = 1
Clock cycle time
CL* = 2
CL* = 3
Clock high time
Clock low time
Access time from CLK
CL* = 1
(positive edge)
CL* = 2
CL* = 3
CAS# to CAS# Delay time
Data output hold time
Data output low impedance
Data output high impedance
Data/Address/Control Input set-up time
Data/Address/Control Input hold time
PowerDown Exit set-up time
Refresh time
* CL is CAS# Latency.
-6I(G)/7I(G)/8I(G)/10I(G)
Min.
Max.
54/63/72/90
16/16/16/30
16/16/16/30
12/14/16/20
36/42/48/60
100,000
1
-20/20/20/30
-7.5/8/8/15
6/7/8/10
2/2.5/3/3.5
2/2.5/3/3.5
1
2/2/2/3
1/1/2/2
2/2/2.5/3
1
6/7/8/10
-8/13/18/27
-6/6.5/7/12
5/5.5/6.5/7.5
4/5/6/8
64
Unit Note
9
9
ns 9
9
Cycle
10
ns 11
11
11
Cycle
10
8
ns 11
11
ms
Note:
1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to
the device.
2. All voltages are referenced to VSS. VIH(Max)=4.6 for pulse width5ns.VIL(Min)=-1.5Vfor pulse width5ns.
3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the
minimum value of tCK and tRC. Input signals are changed one time during tCK.
4. These parameters depend on the output loading. Specified values are obtained with the output open.
5. Power-up sequence is described in Note 12.
Preliminary
19
Rev. 1.1 Apr. 2005
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Overview
The EM636165 SDRAM is a high-speed CMOS synchronous DRAM containing 16 Mbits. It is internally configured as a dual 512K word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 512K x 16 bit banks is organized as 2048 rows by 256 columns by 16 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command.
The EM636165 provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with a burst termination option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. By having a programmable mode register, the system can choose the most suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidth and particularly well suited to high performance PC applications

Features
· Fast access time: 5/5.5/6.5/7.5 ns
· Fast clock rate: 166/143/125/100 MHz
· Self refresh mode: standard and low power
· Internal pipelined architecture
· 512K word x 16-bit x 2-bank
· Programmable Mode registers
   - CAS# Latency: 1, 2, or 3
   - Burst Length: 1, 2, 4, 8, or full page
   - Burst Type: interleaved or linear burst
   - Burst stop function
· Individual byte controlled by LDQM and UDQM
· Auto Refresh and Self Refresh
· 4096 refresh cycles/64ms
· CKE power down mode
· Single +3.3V±0.3V power supply
· Interface: LVTTL
· 50-pin 400 mil plastic TSOP II package
· Lead Free Package available

 

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