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EM636165TS-7I View Datasheet(PDF) - Etron Technology

Part NameEM636165TS-7I Etron
Etron Technology Etron
Description1Mega x 16 Synchronous DRAM (SDRAM)


EM636165TS-7I Datasheet PDF : 73 Pages
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EtronTech
1M x 16 SDRAM EM636165-XXI
Test Mode field (A8~A7)
These two bits are used to enter the test mode and must be programmed to "00" in normal
operation.
A8 A7
Test Mode
0
0
normal mode
0
1
Vendor Use Only
1
X
Vendor Use Only
Single Write Mode (A9)
This bit is used to select the write mode. When the BS bit is "0", the Burst-Read-Burst-
Write mode is selected. When the BS bit is "1", the Burst-Read-Single-Write mode is
selected.
A9
Single Write Mode
0
Burst-Read-Burst-Write
1
Burst-Read-Single-Write
Note: A10 and A11 should stay Lduring mode set cycle.
8 No-Operation command
(RAS# = "H", CAS# = "H", WE# = "H")
The No-Operation command is used to perform a NOP to the SDRAM which is selected (CS#
is Low). This prevents unwanted commands from being registered during idle or wait states.
9 Burst Stop command
(RAS# = "H", CAS# = "H", WE# = "L")
The Burst Stop command is used to terminate either fixed-length or full-page bursts. This
command is only effective in a read/write burst without the auto precharge function. The terminated
read burst ends after a delay equal to the CAS# latency (refer to the following figure). The
termination of a write burst is shown in the following figure.
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
READ A
NOP
NOP
NOP
Burst Stop
NOP
NOP
NOP
NOP
CAS# latency=1
tCK1, DQ's
DOUT A0 DOUT A1
DOUT A2 DOUT A3
The burst ends after a delay equal to the CAS# latency.
CAS# latency=2
tCK2, DQ's
DOUT A0 DOUT A1
DOUT A2 DOUT A3
CAS# latency=3
tCK3, DQ's
DOUT A0 DOUT A1
DOUT A2 DOUT A3
Termination of a Burst Read Operation (Burst Length 4, CAS# Latency = 1, 2, 3)
Preliminary
14
Rev. 1.1 Apr. 2005
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Overview
The EM636165 SDRAM is a high-speed CMOS synchronous DRAM containing 16 Mbits. It is internally configured as a dual 512K word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 512K x 16 bit banks is organized as 2048 rows by 256 columns by 16 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command.
The EM636165 provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with a burst termination option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. By having a programmable mode register, the system can choose the most suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidth and particularly well suited to high performance PC applications

Features
· Fast access time: 5/5.5/6.5/7.5 ns
· Fast clock rate: 166/143/125/100 MHz
· Self refresh mode: standard and low power
· Internal pipelined architecture
· 512K word x 16-bit x 2-bank
· Programmable Mode registers
   - CAS# Latency: 1, 2, or 3
   - Burst Length: 1, 2, 4, 8, or full page
   - Burst Type: interleaved or linear burst
   - Burst stop function
· Individual byte controlled by LDQM and UDQM
· Auto Refresh and Self Refresh
· 4096 refresh cycles/64ms
· CKE power down mode
· Single +3.3V±0.3V power supply
· Interface: LVTTL
· 50-pin 400 mil plastic TSOP II package
· Lead Free Package available

 

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