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EM636165-XXI View Datasheet(PDF) - Etron Technology

Part NameEM636165-XXI Etron
Etron Technology Etron
Description1Mega x 16 Synchronous DRAM (SDRAM)


EM636165-XXI Datasheet PDF : 73 Pages
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EtronTech
1M x 16 SDRAM EM636165-XXI
6 Write and AutoPrecharge command (refer to the following figure)
(RAS# = "H", CAS# = "L", WE# = "L", A11 = V, A10 = "H", A0-A7 = Column Address)
The Write and AutoPrecharge command performs the precharge operation automatically after
the write operation. Once this command is given, any subsequent command can not occur within a
time delay of {(burst length -1) + tWR + tRP(min.)}. At full-page burst, only the write operation is
performed in this command and the auto precharge function is ignored.
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
C OM M A ND
Bank A
Activate
CAS# latency=1
tCK1, DQ's
CAS# latency=2
tCK2, DQ's
CAS# latency=3
tCK3, DQ's
NOP
NOP
Write A
AutoPrecharge
NOP
NOP
NOP
NOP
DIN A0
DIN A1
tDAL
*
DIN A0
DIN A1
tDAL
*
tDAL
DIN A0
DIN A1
*
NOP
tDAL= tWR + tRP
* Begin AutoPrecharge
Bank can be reactivated at completion of tDAL
Burst Write with Auto-Precharge (Burst Length = 2, CAS# Latency = 1, 2, 3)
7 Mode Register Set command
(RAS# = "L", CAS# = "L", WE# = "L", A11 = V, A10 = V, A0-A9 = Register Data)
The mode register stores the data for controlling the various operating modes of SDRAM. The
Mode Register Set command programs the values of CAS# latency, Addressing Mode and Burst
Length in the Mode register to make SDRAM useful for a variety of different applications. The
default values of the Mode Register after power-up are undefined; therefore this command must be
issued at the power-up sequence. The state of pins A0~A9 and A11 in the same cycle is the data
written to the mode register. One clock cycle is required to complete the write in the mode register
(refer to the following figure). The contents of the mode register can be changed using the same
command and the clock cycle requirements during operation as long as both banks are in the idle
state.
Preliminary
11
Rev. 1.1 Apr. 2005
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Overview
The EM636165 SDRAM is a high-speed CMOS synchronous DRAM containing 16 Mbits. It is internally configured as a dual 512K word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 512K x 16 bit banks is organized as 2048 rows by 256 columns by 16 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command.
The EM636165 provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with a burst termination option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. By having a programmable mode register, the system can choose the most suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidth and particularly well suited to high performance PC applications

Features
· Fast access time: 5/5.5/6.5/7.5 ns
· Fast clock rate: 166/143/125/100 MHz
· Self refresh mode: standard and low power
· Internal pipelined architecture
· 512K word x 16-bit x 2-bank
· Programmable Mode registers
   - CAS# Latency: 1, 2, or 3
   - Burst Length: 1, 2, 4, 8, or full page
   - Burst Type: interleaved or linear burst
   - Burst stop function
· Individual byte controlled by LDQM and UDQM
· Auto Refresh and Self Refresh
· 4096 refresh cycles/64ms
· CKE power down mode
· Single +3.3V±0.3V power supply
· Interface: LVTTL
· 50-pin 400 mil plastic TSOP II package
· Lead Free Package available

 

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