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EM636165BE-10G View Datasheet(PDF) - Etron Technology

Part NameEM636165BE-10G Etron
Etron Technology Etron
Description1Mega x 16 Synchronous DRAM (SDRAM)


EM636165BE-10G Datasheet PDF : 75 Pages
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EtronTech
1M x 16 SDRAM
EM636165
The read data appears on the DQs subject to the values on the LDQM/UDQM inputs two clocks
earlier (i.e. LDQM/UDQM latency is two clocks for output buffers). A read burst without the auto
precharge function may be interrupted by a subsequent Read or Write command to the same bank
or the other active bank before the end of the burst length. It may be interrupted by a
BankPrecharge/ PrechargeAll command to the same bank too. The interrupt coming from the Read
command can occur on any clock cycle following a previous Read command (refer to the following
figure).
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
C OM M A ND
READ A
READ B
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CAS# latency=1
tCK1, DQ's
CAS# latency=2
tCK2, DQ's
CAS# latency=3
tCK3, DQ's
DOUT A0 DOUT B0
DOUT B1
DOUT B2
DOUT B3
DOUT A0 DOUT B0
DOUT B1
DOUT B2
DOUT B3
DOUT A0 DOUT B0
DOUT B1
DOUT B2
DOUT B3
Read Interrupted by a Read (Burst Length = 4, CAS# Latency = 1, 2, 3)
The LDQM/UDQM inputs are used to avoid I/O contention on the DQ pins when the interrupt
comes from a Write command. The LDQM/UDQM must be asserted (HIGH) at least two clocks prior
to the Write command to suppress data-out on the DQ pins. To guarantee the DQ pins against I/O
contention, a single cycle with high-impedance on the DQ pins must occur between the last read
data and the Write command (refer to the following three figures). If the data output of the burst
read occurs at the second clock of the burst write, the LDQM/UDQM must be asserted (HIGH) at
least one clock prior to the Write command to avoid internal bus contention.
CLK
DQM
T0
T1
T2
T3
T4
T5
T6
T7
T8
C OM M A ND
NOP
READ A
NOP
NOP
NOP
NOP
WRITE B
NOP
DQ's
: "H" or "L"
DOUT A0
Must be Hi-Z before
the Write Command
DINB0
DINB1
Read to Write Interval (Burst Length 4, CAS# Latency = 3)
NOP
DINB2
Preliminary
8
Rev. 2.7 Mar. 2006
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Overview
The EM636165 SDRAM is a high-speed CMOS synchronous DRAM containing 16 Mbits. It is internally configured as a dual 512K word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 512K x 16 bit banks is organized as 2048 rows by 256 columns by 16 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command.
The EM636165 provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with a burst termination option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. By having a programmable mode register, the system can choose the most suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidth and particularly well suited to high performance PC applications

Features
· Fast access time: 4.5/5/5/5.5/6.5/7.5 ns
· Fast clock rate: 200/183/166/143/125/100 MHz
· Self refresh mode: standard and low power
· Internal pipelined architecture
· 512K word x 16-bit x 2-bank
· Programmable Mode registers
   - CAS# Latency: 1, 2, or 3
   - Burst Length: 1, 2, 4, 8, or full page
   - Burst Type: interleaved or linear burst
   - Burst stop function
· Individual byte controlled by LDQM and UDQM
· Auto Refresh and Self Refresh
· 4096 refresh cycles/64ms
· CKE power down mode
· JEDEC standard +3.3V±0.3V power supply
· Interface: LVTTL
· 50-pin 400 mil plastic TSOP II package
· 60-ball, 6.4x10.1mm VFBGA package
· Lead Free Package available for both TSOP II and VFBGA

 

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