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EM636165TS-7L View Datasheet(PDF) - Etron Technology

Part NameEM636165TS-7L Etron
Etron Technology Etron
Description1Mega x 16 Synchronous DRAM (SDRAM)


EM636165TS-7L Datasheet PDF : 75 Pages
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EtronTech
1M x 16 SDRAM
EM636165
Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CLK.
Table 2 shows the truth table for the operation commands.
Table 2. Truth Table (Note (1), (2) )
Command
State CKEn-1 CKEn DQM(6) A11 A10 A0-9 CS# RAS# CAS# WE#
BankActivate
Idle(3)
H
X
X VV V L L H H
BankPrecharge
Any
HX
X VL X L L H L
PrechargeAll
Any
HX
X XH X L L H L
W rite
Active(3) H
X
X VL V L H L L
Write and AutoPrecharge
Active(3) H
X
X VH V L H L L
Read
Active(3) H
X
X VL V L H L H
Read and Autoprecharge
Active(3) H
X
X VH V L H L H
Mode Register Set
Idle
HX
X
VV V L L
LL
No-Operation
Any
HX
X XX X L H H H
Burst Stop
Active(4) H
X
X XX X L H H L
Device Deselect
Any
HX
X XX X H X X X
AutoRefresh
Idle
HH
X
XX X L L
LH
SelfRefresh Entry
Idle
HL
X
XX X L L
LH
SelfRefresh Exit
Idle
L
H
X XX X H X X X
(SelfRefresh)
LH HH
Clock Suspend Mode Entry
Active H L
X XX X X X X X
Power Down Mode Entry
Any(5)
H
L
X XX X H X X X
LH HH
Clock Suspend Mode Exit
Active L
H
X XX X X X X X
Power Down Mode Exit
Any
L
H
X XX X H X X X
(PowerDown)
LH HH
Data Write/Output Enable
Active H X
L XX X X X X X
Data Mask/Output Disable
Active H
X
H XX X X X
XX
Note:
1. V=Valid X=Don't Care L=Low level H=High level
2. CKEn signal is input level when commands are provided.
CKEn-1 signal is input level one clock cycle before the commands are provided.
3. These are states of bank designated by BS signal.
4. Device state is 1, 2, 4, 8, and full page burst operation.
5. Power Down Mode can not enter in the burst operation.
When this command is asserted in the burst cycle, device state is clock suspend mode.
6. LDQM and UDQM
Preliminary
6
Rev. 2.7 Mar. 2006
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Overview
The EM636165 SDRAM is a high-speed CMOS synchronous DRAM containing 16 Mbits. It is internally configured as a dual 512K word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 512K x 16 bit banks is organized as 2048 rows by 256 columns by 16 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command.
The EM636165 provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with a burst termination option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. By having a programmable mode register, the system can choose the most suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidth and particularly well suited to high performance PC applications

Features
· Fast access time: 4.5/5/5/5.5/6.5/7.5 ns
· Fast clock rate: 200/183/166/143/125/100 MHz
· Self refresh mode: standard and low power
· Internal pipelined architecture
· 512K word x 16-bit x 2-bank
· Programmable Mode registers
   - CAS# Latency: 1, 2, or 3
   - Burst Length: 1, 2, 4, 8, or full page
   - Burst Type: interleaved or linear burst
   - Burst stop function
· Individual byte controlled by LDQM and UDQM
· Auto Refresh and Self Refresh
· 4096 refresh cycles/64ms
· CKE power down mode
· JEDEC standard +3.3V±0.3V power supply
· Interface: LVTTL
· 50-pin 400 mil plastic TSOP II package
· 60-ball, 6.4x10.1mm VFBGA package
· Lead Free Package available for both TSOP II and VFBGA

 

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