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EM636165BE-10G View Datasheet(PDF) - Etron Technology

Part NameEM636165BE-10G Etron
Etron Technology Etron
Description1Mega x 16 Synchronous DRAM (SDRAM)

EM636165BE-10G Datasheet PDF : 75 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
1M x 16 SDRAM
Data Input/Output Mask: LDQM and UDQM are byte specific, nonpersistent
I/O buffer controls. The I/O buffers are placed in a high-z state when
LDQM/UDQM is sampled HIGH. Input data is masked when LDQM/UDQM is
sampled HIGH during a write cycle. Output data is masked (two-clock latency)
when LDQM/UDQM is sampled HIGH during a read cycle. UDQM masks DQ15-
DQ8, and LDQM masks DQ7-DQ0.
DQ0-DQ15 Input/Output Data I/O: The DQ0-15 input and output data are synchronized with the positive
edges of CLK. The I/Os are byte-maskable during Reads and Writes.
No Connect: These pins should be left unconnected.
Supply DQ Power: Provide isolated power to DQs for improved noise immunity.
( 3.3V± 0.3V )
Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity.
Supply Power Supply: +3.3V ± 0.3V
Supply Ground
Rev. 2.7 Mar. 2006
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The EM636165 SDRAM is a high-speed CMOS synchronous DRAM containing 16 Mbits. It is internally configured as a dual 512K word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 512K x 16 bit banks is organized as 2048 rows by 256 columns by 16 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command.
The EM636165 provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with a burst termination option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. By having a programmable mode register, the system can choose the most suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidth and particularly well suited to high performance PC applications

· Fast access time: 4.5/5/5/5.5/6.5/7.5 ns
· Fast clock rate: 200/183/166/143/125/100 MHz
· Self refresh mode: standard and low power
· Internal pipelined architecture
· 512K word x 16-bit x 2-bank
· Programmable Mode registers
   - CAS# Latency: 1, 2, or 3
   - Burst Length: 1, 2, 4, 8, or full page
   - Burst Type: interleaved or linear burst
   - Burst stop function
· Individual byte controlled by LDQM and UDQM
· Auto Refresh and Self Refresh
· 4096 refresh cycles/64ms
· CKE power down mode
· JEDEC standard +3.3V±0.3V power supply
· Interface: LVTTL
· 50-pin 400 mil plastic TSOP II package
· 60-ball, 6.4x10.1mm VFBGA package
· Lead Free Package available for both TSOP II and VFBGA


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