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EM636165BE-10G View Datasheet(PDF) - Etron Technology

Part NameEM636165BE-10G Etron
Etron Technology Etron
Description1Mega x 16 Synchronous DRAM (SDRAM)
EM636165BE-10G Datasheet PDF : 75 Pages
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EtronTech
1M x 16 SDRAM
EM636165
Pin Descriptions
Symbol
CLK
Type
Input
CKE
Input
A11
A0-A10
Input
Input
CS#
Input
RAS#
Input
CAS#
Input
WE#
Input
Table 1. Pin Details of EM636165
Description
Clock: CLK is driven by the system clock. All SDRAM input signals are
sampled on the positive edge of CLK. CLK also increments the internal burst
counter and controls the output registers.
Clock Enable: CKE activates(HIGH) and deactivates(LOW) the CLK signal. If
CKE goes low synchronously with clock(set-up and hold time same as other
inputs), the internal clock is suspended from the next clock cycle and the state
of output and burst address is frozen as long as the CKE remains low. When
both banks are in the idle state, deactivating the clock controls the entry to the
Power Down and Self Refresh modes. CKE is synchronous except after the
device enters Power Down and Self Refresh modes, where CKE becomes
asynchronous until exiting the same mode. The input buffers, including CLK,
are disabled during Power Down and Self Refresh modes, providing low
standby power.
Bank Select: A11(BS) defines to which bank the BankActivate, Read, Write, or
BankPrecharge command is being applied.
Address Inputs: A0-A10 are sampled during the BankActivate command (row
address A0-A10) and Read/Write command (column address A0-A7 with A10
defining Auto Precharge) to select one location out of the 256K available in the
respective bank. During a Precharge command, A10 is sampled to determine if
both banks are to be precharged (A10 = HIGH). The address inputs also provide
the op-code during a Mode Register Set command.
Chip Select: CS# enables (sampled LOW) and disables (sampled HIGH) the
command decoder. All commands are masked when CS# is sampled HIGH.
CS# provides for external bank selection on systems with multiple banks. It is
considered part of the command code.
Row Address Strobe: The RAS# signal defines the operation commands in
conjunction with the CAS# and WE# signals and is latched at the positive edges
of CLK. When RAS# and CS# are asserted "LOW" and CAS# is asserted
"HIGH," either the BankActivate command or the Precharge command is
selected by the WE# signal. When the WE# is asserted "HIGH," the
BankActivate command is selected and the bank designated by BS is turned on
to the active state. When the WE# is asserted "LOW," the Precharge command
is selected and the bank designated by BS is switched to the idle state after the
precharge operation.
Column Address Strobe: The CAS# signal defines the operation commands in
conjunction with the RAS# and WE# signals and is latched at the positive edges
of CLK. When RAS# is held "HIGH" and CS# is asserted "LOW," the column
access is started by asserting CAS# "LOW." Then, the Read or Write command
is selected by asserting WE# "LOW" or "HIGH."
Write Enable: The WE# signal defines the operation commands in conjunction
with the RAS# and CAS# signals and is latched at the positive edges of CLK.
The WE# input is used to select the BankActivate or Precharge command and
Read or Write command.
Preliminary
4
Rev. 2.7 Mar. 2006
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