EtronTech
1M x 16 SDRAM
EM636165
Figure 7.2. Clock Suspension During Burst Write (Using CKE)
(Burst Length=4, CAS# Latency=2)
CLK
CKE
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T2
2
tCK2
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0-A9
RAx
CAx
DQ M
DQ Hi-Z
DAx0
DAx1
DAx2
DAx3
Activate
Command
Bank A
Clock Suspend Clock Suspend
1 Cycle
2 Cycles
W rite
Command
Bank A
Note: CKE to CLK disable/enable = 1 clock
Clock Suspend
3 Cycles
Preliminary
31
Rev. 2.7 Mar. 2006