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EM636165TS-7L View Datasheet(PDF) - Etron Technology

Part NameEM636165TS-7L Etron
Etron Technology Etron
Description1Mega x 16 Synchronous DRAM (SDRAM)

EM636165TS-7L Datasheet PDF : 75 Pages
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1M x 16 SDRAM
6. A.C. Test Conditions
LVTTL Interface
Reference Level of Output Signals
Output Load
Input Signal Levels
Transition Time (Rise and Fall) of Input Signals
Reference Level of Input Signals
1.4V / 1.4V
Reference to the Under Output Load (B)
2.4V / 0.4V
Z0= 50
LVTTL D.C. Test Load (A)
LVTTL A.C. Test Load (B)
7. Transition times are measured between VIH and VIL. Transition(rise and fall) of input signals are in a fixed
slope (1 ns).
8. tHZ defines the time in which the outputs achieve the open circuit condition and are not at reference
9. These parameters account for the number of clock cycle and depend on the operating frequency of the
clock as follows:
the number of clock cycles = specified value of timing/Clock cycle time
(count fractions as a whole number)
10.If clock rising time is longer than 1 ns, ( tR / 2 -0.5) ns should be added to the parameter.
11.Assumed input rise and fall time tT ( tR & tF ) = 1 ns
If tR or tF is longer than 1 ns, transient time compensation should be considered, i.e., [(tr + tf)/2 - 1] ns
should be added to the parameter.
12. Power up Sequence
Power up must be performed in the following sequence.
1) Power must be applied to VDD and VDDQ(simultaneously) when all input signals are held "NOP" state
and both CKE = "H" and LDQM/UDQM = "H." The CLK signals must be started at the same time.
2) After power-up, a pause of 200µseconds minimum is required. Then, it is recommended that
LDQM/UDQM is held "HIGH" (VDD levels) to ensure DQ output is in high impedance.
3) Both banks must be precharged.
4) Mode Register Set command must be asserted to initialize the Mode register.
5) A minimum of 2 Auto-Refresh dummy cycles must be required before or after the Mode Register
Set command in step 4 to stabilize the internal circuitry of the device.
Rev. 2.7 Mar. 2006
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The EM636165 SDRAM is a high-speed CMOS synchronous DRAM containing 16 Mbits. It is internally configured as a dual 512K word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 512K x 16 bit banks is organized as 2048 rows by 256 columns by 16 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command.
The EM636165 provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with a burst termination option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. By having a programmable mode register, the system can choose the most suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidth and particularly well suited to high performance PC applications

· Fast access time: 4.5/5/5/5.5/6.5/7.5 ns
· Fast clock rate: 200/183/166/143/125/100 MHz
· Self refresh mode: standard and low power
· Internal pipelined architecture
· 512K word x 16-bit x 2-bank
· Programmable Mode registers
   - CAS# Latency: 1, 2, or 3
   - Burst Length: 1, 2, 4, 8, or full page
   - Burst Type: interleaved or linear burst
   - Burst stop function
· Individual byte controlled by LDQM and UDQM
· Auto Refresh and Self Refresh
· 4096 refresh cycles/64ms
· CKE power down mode
· JEDEC standard +3.3V±0.3V power supply
· Interface: LVTTL
· 50-pin 400 mil plastic TSOP II package
· 60-ball, 6.4x10.1mm VFBGA package
· Lead Free Package available for both TSOP II and VFBGA


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