1M x 16 SDRAM
Electrical Characteristics and Recommended A.C. Operating Conditions
(VDD = 3.3V±0.3V, Ta = -0~70°C) (Note: 5, 6, 7, 8)
tRC Row cycle time
tRCD RAS# to CAS# delay
tRP Precharge to refresh/row activate
command (same bank)
tRRD Row activate to row activate delay
tRAS Row activate to precharge time
tWR Write recovery time
CL* = 1 -/19/20/20/20/20/30
tCK2 Clock cycle time
CL* = 2 -/7/7.5/8/8/8/15
CL* = 3 5/5.5/6/7/7/8/10
tCH Clock high time
Clock low time
tAC1 Access time from CLK
CL* = 1
tAC2 (positive edge)
CL* = 2
CL* = 3
tCCD CAS# to CAS# Delay time
tOH Data output hold time
Data output low impedance
tHZ Data output high impedance
Data/Address/Control Input set-up time
Data/Address/Control Input hold time
tPDE PowerDown Exit set-up time
tREF Refresh time
* CL is CAS# Latency.
1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to
2. All voltages are referenced to VSS. VIH(Max)=4.6 for pulse width≤5ns.VIL(Min)=-1.5Vfor pulse width≤5ns.
3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the
minimum value of tCK and tRC. Input signals are changed one time during tCK.
4. These parameters depend on the output loading. Specified values are obtained with the output open.
5. Power-up sequence is described in Note 12.
Rev. 2.7 Mar. 2006