EtronTech

1M x 16 SDRAM

EM636165

• Addressing Mode Select Field (A3)

The Addressing Mode can be one of two modes, Interleave Mode or Sequential Mode.

Sequential Mode supports burst length of 1, 2, 4, 8, or full page, but Interleave Mode only

supports burst length of 4 and 8.

A3

Addressing Mode

0

Sequential

1

Interleave

--- Addressing Sequence of Sequential Mode

An internal column address is performed by increasing the address from the column

address which is input to the device. The internal column address is varied by the Burst

Length as shown in the following table. When the value of column address, (n + m), in

the table is larger than 255, only the least significant 8 bits are effective.

Data n

0 1 2 3 4 5 6 7 - 255 256 257 -

Column Address n n+1 n+2 n+3 n+4 n+5 n+6 n+7 - n+255 n n+1 -

Burst Length

2 words:

4 words:

8 words:

Full Page: Column address is repeated until terminated.

--- Addressing Sequence of Interleave Mode

A column access is started in the input column address and is performed by inverting

the address bits in the sequence shown in the following table.

Data n

Column Address

Data 0 A7 A6 A5 A4 A3 A2 A1 A0

Data 1 A7 A6 A5 A4 A3 A2 A1 A0#

Data 2 A7 A6 A5 A4 A3 A2 A1# A0

Data 3 A7 A6 A5 A4 A3 A2 A1# A0#

Data 4 A7 A6 A5 A4 A3 A2# A1 A0

Data 5 A7 A6 A5 A4 A3 A2# A1 A0#

Data 6 A7 A6 A5 A4 A3 A2# A1# A0

Data 7 A7 A6 A5 A4 A3 A2# A1# A0#

Burst Length

4 words

8 words

• CAS# Latency Field (A6~A4)

This field specifies the number of clock cycles from the assertion of the Read command to

the first read data. The minimum whole value of CAS# Latency depends on the frequency

of CLK. The minimum whole value satisfying the following formula must be programmed

into this field.

tCAC(min) ≤ CAS# Latency X tCK

A6

A5

A4 CAS# Latency

0

0

0

Reserved

0

0

1

1 clock

0

1

0

2 clocks

0

1

1

3 clocks

1

X

X

Reserved

Preliminary

14

Rev. 2.7 Mar. 2006