|Description||1Mega x 16 Synchronous DRAM (SDRAM)|
|EM636165BE-10G Datasheet PDF : 75 Pages |
1M x 16 SDRAM
The Read command that interrupts a write burst without auto precharge function should be
issued one cycle after the clock edge in which the last data-in element is registered. In order to
avoid data contention, input data must be removed from the DQs at least one clock cycle before the
first read data appears on the outputs (refer to the following figure). Once the Read command is
registered, the data inputs will be ignored and writes will not be executed.
WRITE A READ B
DOUT B0 DOUT B1
DOUT B2 DOUT B3
DOUT B2 DOUT B3
don't care don't care
Input data for the write is masked.
DOUT B1 DOUT B2 DOUT B3
Input data must be removed from the DQ's at least one clock
cycle before the Read data appears on the outputs to avoid
Write Interrupted by a Read (Burst Length = 4, CAS# Latency = 1, 2, 3)
The BankPrecharge/PrechargeAll command that interrupts a write burst without the auto
precharge function should be issued m cycles after the clock edge in which the last data-in element
is registered, where m equals tWR/tCK rounded up to the next whole number. In addition, the
LDQM/UDQM signals must be used to mask input data, starting with the clock edge following the
last data-in element and ending with the clock edge on which the BankPrecharge/PrechargeAll
command is entered (refer to the following figure).
C OM M A ND
: don't care
Note: The LDQM/UDQM can remain low in this example if the length of the write burst is 1 or 2.
Write to Precharge
Rev. 2.7 Mar. 2006
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