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C052G View Datasheet(PDF) - KEMET

Part NameC052G Kemet

C052G Datasheet PDF : 14 Pages
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Power dissipation has been empirically determined for
two representative KEMET series: C052 and C062. Power dis-
sipation capability for various mounting configurations is shown
in Table 3. This table was extracted from Engineering Bulletin
F-2013, which provides a more detailed treatment of this sub-
Note that no significant difference was detected between
the two sizes in spite of a 2 to 1 surface area ratio. Due to the
materials used in the construction of multilayer ceramic capac-
itors, the power dissipation capability does not depend greatly
on the surface area of the capacitor body, but rather on how
well heat is conducted out of the capacitor lead wires.
Consequently, this power dissipation capability is applicable to
other leaded multilayer styles and sizes.
(Rise in Celsius degrees per Watt)
Mounting Configuration
of C052 & C062
1.00" leadwires attached to binding post
of GR-1615 bridge (excellent heat sink)
90 Celsius degrees
rise per Watt ±10%
0.25" leadwires attached to binding post
of GR-1615 bridge
55 Celsius degrees
rise per Watt ±10%
Capacitor mounted flush to 0.062" glass-
epoxy circuit board with small copper traces
77 Celsius degrees
rise per Watt ±10%
Capacitor mounted flush to 0.062" glass-
epoxy circuit board with four square inches
of copper land area as a heat sink
53 Celsius degrees
rise per Watt ±10%
As shown in Table 3, the power dissipation capability of
the capacitor is very sensitive to the details of its use environ-
ment. The temperature rise due to power dissipation should not
exceed 20°C. Using that constraint, the maximum permissible
power dissipation may be calculated from the data provided in
Table 3.
It is often convenient to translate power dissipation capa-
bility into a permissible AC voltage rating. Assuming a sinu-
soidal wave form, the RMS “ripple voltage” may be calculated
from the following formula:
Where E = RMS Ripple Voltage (volts)
P = Power Dissipation (watts)
Z = Impedance
The data necessary to make this calculation is included in
Engineering Bulletin F-2013. However, the following criteria
must be observed:
1. The temperature rise due to power dissipation
should be limited to 20°C.
2. The peak AC voltage plus the DC voltage must not
exceed the maximum working voltage of the
Provided that these criteria are met, multilayer ceramic
capacitors may be operated with AC voltage applied without
need for DC bias.
A well constructed multilayer ceramic capacitor is
extremely reliable and, for all practical purposes, has an infi-
nite life span when used within the maximum voltage and
temperature ratings. Capacitor failure may be induced by sus-
tained operation at voltages that exceed the rated DC voltage,
voltage spikes or transients that exceed the dielectric with-
standing voltage, sustained operation at temperatures above
the maximum rated temperature, or the excessive tempera-
ture rise due to power dissipation.
Failure rate is usually expressed in terms of percent per
1,000 hours or in FITS (failure per billion hours). Some
KEMET series are qualified under U.S. military established
reliability specifications MIL-PRF-20, MIL-PRF-123, MIL-
PRF-39014, and MIL-PRF-55681. Failure rates as low as
0.001% per 1,000 hours are available for all capacitance /
voltage ratings covered by these specifications. These spec-
ifications and accompanying Qualified Products List should
be consulted for details.
For series not covered by these military specifications,
an internal testing program is maintained by KEMET Quality
Assurance. Samples from each week’s production are sub-
jected to a 2,000 hour accelerated life test at 2 x rated voltage
and maximum rated temperature. Based on the results of
these tests, the average failure rate for all non-military series
covered by this test program is currently 0.06% per 1,000
hours at maximum rated conditions. The failure rate would be
much lower at typical use conditions. For example, using MIL-
HDBK-217D this failure rate translates to 0.9 FITS at 50%
rated voltage and 50°C.
Current failure rate details for specific KEMET multilay-
er ceramic capacitor series are available on request.
Ceramic capacitors, like any other capacitors, may fail
if they are misapplied. Typical misapplications include expo-
sure to excessive voltage, current or temperature. If the
dielectric layer of the capacitor is damaged by misapplication
the electrical energy of the circuit can be released as heat,
which may damage the circuit board and other components
as well.
If potential for misapplication exists, it is recommended
that precautions be taken to protect personnel and equipment
during initial application of voltage. Commonly used precau-
tions include shielding of personnel and sensing for excessive
power drain during board testing.
Ceramic chip capacitors should be stored in normal
working environments. While the chips themselves are quite
robust in other environments, solderability will be degraded
by exposure to high temperatures, high humidity, corrosive
atmospheres, and long term storage. In addition, packaging
materials will be degraded by high temperature – reels may
soften or warp, and tape peel force may increase. KEMET
recommends that maximum storage temperature not exceed
40˚ C, and maximum storage humidity not exceed 70% rela-
tive humidity. In addition, temperature fluctuations should be
minimized to avoid condensation on the parts, and atmos-
pheres should be free of chlorine and sulfur bearing com-
pounds. For optimized solderability, chip stock should be
used promptly, preferably within 1.5 years of receipt.
© KEMET Electronics Corporation, P.O. Box 5928, Greenville, S.C. 29606, (864) 963-6300
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Multilayer ceramic capacitors are available in a variety of physical sizes and configurations, including leaded devices and surface mounted chips. Leaded styles include molded and conformally coated parts with axial and radial leads. However, the basic capacitor element is similar for all styles. It is called a chip and consists of formulated dielectric materials which have been cast into thin layers, interspersed with metal electrodes alternately exposed on opposite edges of the laminated structure. The entire structure is fired at high temperature to produce a monolithic block which provides high capacitance values in a small physical volume. After firing, conductive terminations are applied to opposite ends of the chip to make contact with the exposed electrodes. Termination materials and methods vary depending on the intended use.


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