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AD9058JD View Datasheet(PDF) - Analog Devices

Part Name
Description
Manufacturer
AD9058JD
ADI
Analog Devices ADI
AD9058JD Datasheet PDF : 8 Pages
1 2 3 4 5 6 7 8
AD9058
Parameter (Conditions)
Test
AD9058JD/JJ
AD9058KD/KJ
Temp Level Min Typ Max Min Typ Max Unit
DYNAMIC PERFORMANCE
Transient Response
+25°C V
Overvoltage Recovery Time
+25°C V
Effective Number of Bits (ENOB)5
Analog Input @ 2.3 MHz
+25°C I
@ 10.3 MHz
+25°C I
Signal-to-Noise Ratio5
Analog Input @ 2.3 MHz
+25°C I
@ 10.3 MHz
+25°C I
Signal-to-Noise Ratio5 (Without Harmonics)
Analog Input @ 2.3 MHz
+25°C I
@ 10.3 MHz
+25°C I
2nd Harmonic Distortion
Analog Input @ 2.3 MHz
+25°C I
@ 10.3 MHz
+25°C I
3rd Harmonic Distortion
Analog Input @ 2.3 MHz
+25°C I
@ 10.3 MHz
+25°C I
Crosstalk Rejection6
+25°C IV
2
2
ns
2
2
ns
7.7
7.2 7.7
Bits
7.4
7.1 7.4
Bits
48
45 48
dB
46
44 46
dB
48
46 48
dB
47
45 47
dB
58
48 58
dBc
58
48 58
dBc
58
50 58
dBc
58
50 58
dBc
60
48 60
dBc
DIGITAL OUTPUTS
Logic “1” Voltage (IOH = 2 mA)
Logic “0” Voltage (IOL = 2 mA)
POWER SUPPLY7
+VS Supply Current
–VS Supply Current
Power Dissipation
Full VI
Full VI
Full VI
Full VI
Full VI
2.4
2.4
V
0.4
0.4 V
127 154
27 38
770 960
127 154 mA
27 38
mA
770 960 mW
NOTES
1Absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is
not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability.
2For applications in which +VS may be applied before –VS, or +VS current is not limited to 500 mA, a reverse biased clamping diode should be inserted between
ground and –VS to prevent destructive latch up. See section entitled “Using the AD9058.”
3Typical thermal impedances: 44-lead hermetic J-Leaded ceramic package: θJA = 86.4°C/W; θJC = 24.9°C/W; 48-lead hermetic DIP θJA = 40°C/W;
θJC = 12°C/W.
4To achieve guaranteed conversion rate, connect each data output to ground through a 2 k pull-down resistor.
5SNR performance limits for the 48-lead DIP “D” package are 1 dB less than shown. ENOB limits are degraded by 0.3 dB. SNR and ENOB measured with
analog input signal 1 dB below full scale at specified frequency.
6Crosstalk rejection measured with full-scale signals of different frequencies (2.3 MHz and 3.5 MHz) applied to each channel. With both signals synchronously
encoded at 40 MSPS, isolation of the undesired frequency is measured with an FFT.
7Applies to both A/Ss and includes internal ladder dissipation.
Specifications subject to change without notice.
EXPLANATION OF TEST LEVELS
Test Level
I – 100% production tested.
II – 100% production tested at +25°C, and sample tested at
specified temperatures.
III – Sample tested only.
IV – Parameter is guaranteed by design and characterization
testing.
V – Parameter is a typical value only.
VI – All devices are 100% production tested at +25°C. 100%
production tested at temperature extremes for extended
temperature devices; sample tested at temperature
extremes for commercial/industrial devices.
ORDERING GUIDE
Model
Temperature
Range
Description
Package
Option1
AD9058JJ
0°C to +70°C 44-Lead J-Leaded J-44
Ceramic2
AD9058KJ
0°C to +70°C 44-Lead J-Leaded J-44
Ceramic, AC Tested
AD9058TJ/8833 –55°C to +125°C 44-Lead J-Leaded J-44
Ceramic, AC Tested
AD9058JD
0°C to +70°C 48-Lead Ceramic DIP D-48
AD9058KD
0°C to +70°C 48-Lead Ceramic
D-48
DIP, AC Tested
AD9058TD/8833 –55°C to +125°C 48-Lead Ceramic
D-48
DIP, AC Tested
NOTES
1D = Hermetic Ceramic DIP Package; J = Leaded Ceramic Package.
2Hermetically sealed ceramic package; footprint equivalent to PLCC.
3For specifications, refer to Analog Devices Military Products Databook.
REV. B
–3–
 

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