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LF13201M Просмотр технического описания (PDF) - National ->Texas Instruments

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LF13201M Quad SPST JFET Analog Switches NSC
National ->Texas Instruments NSC
LF13201M Datasheet PDF : 18 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Typical Performance Characteristics (Continued)
Slew Rate of Analog
Voltage Above Which
Signal Loading Occurs
Small Signal Response
Maximum Accurate
Analog Current
vs Temperature
Logical “1” Input Bias
Application Hints
These devices are monolithic quad JFET analog switches
with “ON” resistances which are essentially independent of
analog voltage or analog current. The leakage currents are
typically less than 1 nA at 25˚C in both the “OFF”and “ON”
switch states and introduce negligible errors in most applica-
tions. Each switch is controlled by minimum TTL logic levels
at its input and is designed to turn “OFF” faster than it will
turn “ON.” This prevents two analog sources from being tran-
siently connected together during switching. The switches
were designed for applications which require
break-before-make action, no analog current loss, medium
speed switching times and moderate analog currents.
Because these analog switches are JFET rather than
CMOS, they do not require special handling.
The logic input (IN), of each switch, is referenced to two for-
ward diode drops (1.4V at 25˚C) from the reference supply
(VR) which makes it compatible with DTL, RTL, and TTL
logic families. For normal operation, the logic “0” voltage can
range from 0.8V to −4.0V with respect to VR and the logic “1”
voltage can range from 2.0V to 6.0V with respect to VR, pro-
vided VIN is not greater than (VCC−2.5V). If the input voltage
is greater than (VCC−2.5V), the input current will increase. If
the input voltage exceeds 6.0V or −4.0V with respect to VR,
a resistor in series with the input should be used to limit the
input current to less than 100µA.
Analog Voltage
Each switch has a constant “ON” resistance (RON) for analog
voltages from (VEE+5V) to (VCC−5V). For analog voltages
greater than (VCC−5V), the switch will remain ON indepen-
dent of the logic input voltage. For analog voltages less than
(VEE+5V), the ON resistance of the switch will increase. Al-
though the switch will not operate normally when the analog
voltage is out of the previously mentioned range, the source
voltage can go to either (VEE+36V) or (VCC+6V), whichever
is more positive, and can go as negative as VEE without de-
struction. The drain (D) voltage can also go to either
(VEE+36V) or (VCC+6V), whichever is more positive, and can
go as negative as (VCC−36V) without destruction.
Analog Current
With the source (S) positive with respect to the drain (D), the
RON is constant for low analog currents, but will increase at
higher currents (>5 mA) when the FET enters the saturation
region. However, if the drain is positive with respect to the
source and a small analog current loss at high analog cur-
rents (Note 6) is tolerable, a low RON can be maintained for
analog currents greater than 5 mA at 25˚C.
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