ML145162
LANSDALE Semiconductor, Inc.
POWER SAVING OPERATION
This PLL has a programmable power–saving scheme. The
transmit and receive counters and the reference frequency
counter can be powered down individually by setting the TxPD
enable, RxPD enable, and Ref PD enable bits of the control
register. The functions of the power down control bits are
explained in Table 2 and the programming format is in Figure 8.
The output pins TxPS/fTx and RxPS/fRx output the status of
the internal power saving setting. If the bit TxPD enable is set
“high” (transmit counter is set to power–down mode), then the
TxPS/fTx pin will also output a “high” state. This TxPS/fTx
out-put can control an external power switch to switch off the
transmitter, as shown in Figure 17. This scheme can be applied
to the RxPS/fRx output to control the receiver power saving
operation as required.
POWER SUPPLY
TxPS/fTx
UNIVERSAL DUAL PLL
VDD
POWER SWITCH FOR TRANSMITTER
Tx POWER–DOWN
Q
ENABLE FLAG
Tx DIVIDER CHAIN COUNTER, PHASE DETECTOR
Tx
POWER
AMP
RxPS/fRx
VDD
Q Rx POWER–DOWN
ENABLE FLAG
TO CONTROL THE RECEIVER
POWER SWITCH
Rx DIVIDER CHAIN COUNTER, PHASE DETECTOR
Figure 17. TxPS/fTx and RxPS/fRx Outputs to Control Power Switches
of the Transmitter and the Receiver
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