STM32F103C6 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STM32F103C6

Performance line, ARM-based 32-bit MCU with Flash, USB, CAN, seven 16-bit timers, two ADCs and nine communication interfaces

STMicroelectronics 

Electrical characteristics

STM32F103xx

5.3.8

Wakeup time from low power mode

The wakeup times given in Table 21 is measured on a wakeup phase with a 8-MHz HSI RC

oscillator. The clock source used to wake up the device depends from the current operating

mode:

● Stop or Standby mode: the clock source is the RC oscillator

● Sleep mode: the clock source is the clock that was set before entering Sleep mode.

All timings are derived from tests performed under ambient temperature and VDD supply

voltage conditions summarized in Table 7.

Table 21. Low-power mode wakeup timings(1)

Symbol

Parameter

Conditions

Typ Max Unit

tWUSLEEP(2) Wakeup from Sleep mode

Wakeup on HSI RC clock

0.75 TBD µs

tWUSTOP(2)

Wakeup from Stop mode

(regulator in run mode)

Wakeup from Stop mode

(regulator in low power mode)

HSI RC wakeup time = 2 µs

HSI RC wakeup time = 2 µs,

Regulator wakeup from LP

mode time = 5 µs

4 TBD

µs

7 TBD

tWUSTDBY(3) Wakeup from Standby mode

HSI RC wakeup time = 2 µs,

Regulator wakeup from power

down time = 38 µs

40 TBD µs

1. TBD stands for to be determined.

2. The wakeup time from Sleep and Stop mode are measured from the wakeup event to the point in which the

user application code reads the first instruction.

3. The wakeup time from Standby mode is measured from the wakeup event to the point in which the device

exits from reset.

PLL characteristics

The parameters given in Table 22 are derived from tests performed under ambient

temperature and VDD supply voltage conditions summarized in Table 7.

Table 22. PLL characteristics(1)

Symbol

Parameter

Value

Test Conditions

Min Typ Max(2)

fPLL_IN

PLL input clock

PLL input clock duty cycle

8.0

40

fPLL_OUT PLL multiplier output clock

16

fVCO VCO frequency range

When PLL operates

(locked)

32

tLOCK

tJITTER

PLL lock time

Cycle to cycle jitter (+/-3Σ

peak to peak)

VDD is stable

TBD

60

72

144

200

TBD

1. TBD stands for to be determined.

2. Data based on device characterization, not tested in production.

Unit

MHz

%

MHz

MHz

µs

%

38/67

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