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54F373FMX 查看數據表(PDF) - National ->Texas Instruments

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54F373FMX Octal Transparent Latch with TRI-STATEÉ Outputs National-Semiconductor
National ->Texas Instruments National-Semiconductor
54F373FMX Datasheet PDF : 9 Pages
1 2 3 4 5 6 7 8 9
Unit Loading Fan Out
Pin Names
Description
D0 – D7
LE
OE
O0 – O7
Data Inputs
Latch Enable Input (Active HIGH)
Output Enable Input (Active LOW)
TRI-STATE Latch Outputs
54F 74F
UL
HIGH LOW
10 10
10 10
10 10
150 40 (33 3)
Input IIH IIL
Output IOH IOL
20 mA b0 6 mA
20 mA b0 6 mA
20 mA b0 6 mA
b3 mA 24 mA (20 mA)
Functional Description
The ’F373 contains eight D-type latches with TRI-STATE
output buffers When the Latch Enable (LE) input is HIGH
data on the Dn inputs enters the latches In this condition
the latches are transparent i e a latch output will change
state each time its D input changes When LE is LOW the
latches store the information that was present on the D in-
puts a setup time preceding the HIGH-to-LOW transition of
LE The TRI-STATE buffers are controlled by the Output
Enable (OE) input When OE is LOW the buffers are in the
bi-state mode When OE is HIGH the buffers are in the high
impedance mode but this does not interfere with entering
new data into the latches
Truth Table
Inputs
LE
OE
Dn
H
L
H
H
L
L
L
L
X
X
H
X
H e HIGH Voltage Level
L e LOW Voltage Level
X e Immaterial
Z e High Impedance State
Logic Diagram
Output
On
H
L
On (no change)
Z
TL F 9523 – 5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
2
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