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AD2S1210-EP View Datasheet(PDF) - Analog Devices

Part Name
Description
Manufacturer
AD2S1210-EP Datasheet PDF : 16 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
TIMING SPECIFICATIONS
AVDD = DVDD = 5.0 V ± 5%, TA = TMIN to TMAX, unless otherwise noted.1
Table 2.
Parameter
fCLKIN
Description
Frequency of clock input
tCK
Clock period (tCK = 1/fCLKIN)
t1
A0 and A1 setup time before RD/CS low
t2
Delay CS falling edge to WR/FSYNC rising edge
t3
Address/data setup time during a write cycle
t4
Address/data hold time during a write cycle
t5
Delay WR/FSYNC rising edge to CS rising edge
t6
Delay CS rising edge to CS falling edge
t7
Delay between writing address and writing data
t8
A0 and A1 hold time after WR/FSYNC rising edge
t9
Delay between successive write cycles
t10
Delay between rising edge of WR/FSYNC and falling edge of RD
t11
Delay CS falling edge to RD falling edge
t12
Enable delay RD low to data valid in configuration mode
VDRIVE = 4.5 V to 5.25 V
VDRIVE = 2.7 V to 3.6 V
VDRIVE = 2.3 V to 2.7 V
t13
RD rising edge to CS rising edge
t14A
Disable delay RD high to data high-Z
t14B
Disable delay CS high to data high-Z
t15
Delay between rising edge of RD and falling edge of WR/FSYNC
t16
SAMPLE pulse width
t17
Delay from SAMPLE before RD/CS low
t18
Hold time RD before RD low
t19
Enable delay RD/CS low to data valid
VDRIVE = 4.5 V to 5.25 V
VDRIVE = 2.7 V to 3.6 V
VDRIVE = 2.3 V to 2.7 V
t20
RD pulse width
t21
A0 and A1 set time to data valid when RD/CS low
VDRIVE = 4.5 V to 5.25 V
VDRIVE = 2.7 V to 3.6 V
VDRIVE = 2.3 V to 2.7 V
t22
Delay WR/FSYNC falling edge to SCLK rising edge
t23
Delay WR/FSYNC falling edge to SDO release from high-Z
VDRIVE = 4.5 V to 5.25 V
VDRIVE = 2.7 V to 3.6 V
VDRIVE = 2.3 V to 2.7 V
t24
Delay SCLK rising edge to DBx valid
VDRIVE = 4.5 V to 5.25 V
VDRIVE = 2.7 V to 3.6 V
VDRIVE = 2.3 V to 2.7 V
t25
SCLK high time
t26
SCLK low time
t27
SDI setup time prior to SCLK falling edge
t28
SDI hold time after SCLK falling edge
Rev. 0 | Page 5 of 16
AD2S1210-EP
Limit at TMIN, TMAX
6.144
10.24
98
163
2
22
3
2
2
10
2 × tCK + 20
2
6 × tCK + 20
2
2
37
25
30
2
16
16
2
2 × tCK + 20
6 × tCK + 20
2
17
21
33
6
36
37
29
3
16
26
29
24
18
32
0.4 × tSCLK
0.4 × tSCLK
3
2
Unit
MHz min
MHz max
ns min
ns max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
 

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