W631GG6KB View Datasheet(PDF) - Winbond

Part Name

Description

Manufacturer

W631GG6KB

1G bits DDR3 SDRAM, organized as 8,388,608 words x 8 banks x 16 bits.

Winbond 

W631GG6KB

7.7.2 DLL “off” to DLL “on” Procedure

To switch from DLL ―off‖ to DLL ―on‖ (with required frequency change) during Self-Refresh:

1. Starting from Idle state (All banks pre-charged, all timings fulfilled and DRAMs On-die Termination

resistors (RTT) must be in high impedance state before Self-Refresh mode is entered.)

2. Enter Self Refresh Mode, wait until tCKSRE satisfied.

3. Change frequency, in guidance with section 7.8 “Input clock frequency change” on page 27.

4. Wait until a stable clock is available for at least (tCKSRX) at DRAM inputs.

5. Starting with the Self Refresh Exit command, CKE must continuously be registered HIGH until

tDLLK timing from subsequent DLL Reset command is satisfied. In addition, if any ODT features

were enabled in the mode registers when Self Refresh mode was entered, the ODT signal must

continuously be registered LOW until tDLLK timings from subsequent DLL Reset command is

satisfied. If both ODT features are disabled in the mode registers when Self Refresh mode was

entered, ODT signal can be registered LOW or HIGH.

6. Wait tXS, then set MR1 bit A0 to ―0‖ to enable the DLL.

7. Wait tMRD, then set MR0 bit A8 to ―1‖ to start DLL Reset.

8. Wait tMRD, then set Mode Registers with appropriate values (especially an update of CL, CWL and

WR may be necessary. After tMOD satisfied from any proceeding MRS command, a ZQCL

command may also be issued during or after tDLLK.)

9. Wait for tMOD, then DRAM is ready for next command (Remember to wait tDLLK after DLL Reset

before applying command requiring a locked DLL!). In addition, wait also for tZQoper in case a

ZQCL command was issued.

T0

CK#

CK

Ta0

Ta1

Tb0

Tc0

Tc1

Td0

Te0

Tf1

Tg0

Th0

CKE

Command

NOP

SRE*2

NOP

SRX*5

MRS*6

MRS*7

tDLLK

MRS*8

VALID

VALID*9

*1

ODTLoff + 1 x tCK

tCKSRE

*3

tCKSRX*4

tXS

tMRD

tMRD

ODT

tCKESR

ODT: Static LOW in case Rtt_Nom and Rtt_WR is enabled, otherwise static Low or High

Notes:

1. Starting with idle state

2. Enter SR

3. Change Frequency

4. Clock must be stable tCKSRX

5. Exit SR

6. Set DLL on by MR1 A0 = 0

7. Update Mode registers

8. Any valid command

TIME BREAK

DON'T CARE

Figure 11 – DLL Switch Sequence from DLL Off to DLL On

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Publication Release Date: Feb. 27, 2013

Revision A04

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