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ISL12022MIBZ View Datasheet(PDF) - Intersil

Part Name
Description
Manufacturer
ISL12022MIBZ Datasheet PDF : 27 Pages
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ISL12022M
Power-Down Timing
SYMBOL
Test Conditions: VDD = +2.7 to +5.5V, Temperature = -40°C to +85°C, unless otherwise stated.
PARAMETER
CONDITIONS
MIN
TYP
MAX
(Note 10) (Note 6) (Note 10) UNITS
VDDSR-
VDD Negative Slew Rate
10
V/ms
NOTES
7
I2C Interface Specifications Test Conditions: VDD = +2.7 to +5.5V, Temperature = -40°C to +85°C,
unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
(Note 10) (Note 6) (Note 10) UNITS
VIL
SDA and SCL Input Buffer LOW
Voltage
-0.3
0.3 x VDD V
VIH
SDA and SCL Input Buffer HIGH
Voltage
0.7 x VDD
VDD + 0.3 V
Hysteresis
VOL
SDA and SCL Input Buffer
Hysteresis
SDA Output Buffer LOW Voltage, VDD = 5V, IOL = 3mA
Sinking 3mA
0.05 x
V
VDD
0
0.02
0.4
V
CPIN
fSCL
tIN
SDA and SCL Pin Capacitance
SCL Frequency
TA = +25°C, f = 1MHz,
VDD = 5V, VIN = 0V,
VOUT = 0V
Pulse Width Suppression Time at Any pulse narrower than the
SDA and SCL Inputs
max spec is suppressed.
10
pF
400
kHz
50
ns
tAA
SCL Falling Edge to SDA Output SCL falling edge crossing
Data Valid
30% of VDD, until SDA exits
the 30% to 70% of VDD
window.
900
ns
tBUF
Time the Bus Must be Free Before SDA crossing 70% of VDD
1300
ns
the Start of a New Transmission during a STOP condition, to
SDA crossing 70% of VDD
during the following START
condition.
tLOW
Clock LOW Time
Measured at the 30% of VDD
1300
ns
crossing.
tHIGH
Clock HIGH Time
Measured at the 70% of VDD
600
ns
crossing.
tSU:STA
START Condition Setup Time
SCL rising edge to SDA
600
falling edge. Both crossing
70% of VDD.
tHD:STA
START Condition Hold Time
From SDA falling edge
600
crossing 30% of VDD to SCL
falling edge crossing 70% of
VDD.
tSU:DAT
Input Data Setup Time
From SDA exiting the 30% to
100
70% of VDD window, to SCL
rising edge crossing 30% of
VDD.
tHD:DAT
Input Data Hold Time
From SCL falling edge
20
crossing 30% of VDD to SDA
entering the 30% to 70% of
VDD window.
ns
ns
ns
900
ns
NOTES
8, 9
8, 9
4
FN6668.5
July 10, 2009
 

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