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M1A3P1000-1FG144M View Datasheet(PDF) - Actel Corporation

Part NameDescriptionManufacturer
M1A3P1000-1FG144M Military ProASIC3/EL Low-Power Flash FPGAs with Flash*Freeze Technology ACTEL
Actel Corporation ACTEL
M1A3P1000-1FG144M Datasheet PDF : 181 Pages
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Military ProASIC3/EL Device Family Overview
Flash Advantages
Low Powerƒ
The military ProASIC3EL family of Actel flash-based FPGAs provides a low-power advantage, and
when coupled with high performance, enables designers to make power-smart choices using a
single-chip, reprogrammable, and live-at-power-up device.
Military ProASIC3EL devices offer 40% dynamic power and 50% static power savings by reducing
the core operating voltage to 1.2 V. In addition, the power-driven layout (PDL) feature in Libero®
Integrated Design Environment (IDE) offers up to 30% additional power reduction. With
Flash*Freeze technology, military ProASIC3EL device is able to retain device SRAM and logic while
dynamic power is reduced to a minimum, without the need to stop clock or power supplies.
Combining these features provides a low-power, feature-rich, and high-performance solution.
Nonvolatile, flash-based military ProASIC3/EL devices do not require a boot PROM, so there is no
vulnerable external bitstream that can be easily copied. Military ProASIC3/EL devices incorporate
FlashLock, which provides a unique combination of reprogrammability and design security without
external overhead, advantages that only an FPGA with nonvolatile flash programming can offer.
Military ProASIC3/EL devices utilize a 128-bit flash-based lock and a separate AES key to secure
programmed intellectual property and configuration data. In addition, all FlashROM data in
military ProASIC3/EL devices can be encrypted prior to loading, using the industry-leading AES-128
(FIPS192) bit block cipher encryption standard. AES was adopted by the National Institute of
Standards and Technology (NIST) in 2000 and replaces the 1977 DES standard. Military ProASIC3/EL
devices have a built-in AES decryption engine and a flash-based AES key that make them the most
comprehensive programmable logic device security solution available today. Military ProASIC3/EL
devices with AES-based security allow for secure, remote field updates over public networks such as
the Internet, and ensure that valuable IP remains out of the hands of system overbuilders, system
cloners, and IP thieves. The contents of a programmed device cannot be read back, although secure
design verification is possible.
Security, built into the FPGA fabric, is an inherent component of the military ProASIC3/EL family.
The flash cells are located beneath seven metal layers, and many device design and layout
techniques have been used to make invasive attacks extremely difficult. The military ProASIC3/EL
family, with FlashLock and AES security, is unique in being highly resistant to both invasive and
noninvasive attacks. Your valuable IP is protected and secure, making remote ISP possible. A
military ProASIC3/EL device provides the most impenetrable security for programmable logic
Single Chip
Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed,
the configuration data is an inherent part of the FPGA structure, and no external configuration
data needs to be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based
military ProASIC3/EL FPGAs do not require system configuration components such as EEPROMs or
microcontrollers to load device configuration data. This reduces bill-of-materials costs and PCB
area, and increases security and system reliability.
Live at Power-Up
Actel flash-based military ProASIC3/EL devices support Level 0 of the LAPU classification standard.
This feature helps in system component initialization, execution of critical tasks before the
processor wakes up, setup and configuration of memory blocks, clock generation, and bus activity
management. The LAPU feature of flash-based military ProASIC3/EL devices greatly simplifies total
system design and reduces total system cost, often eliminating the need for CPLDs and clock
generation PLLs. In addition, glitches and brownouts in system power will not corrupt the military
ProASIC3/EL device's flash configuration, and unlike SRAM-based FPGAs, the device will not have to
be reloaded when system power is restored. This enables the reduction or complete removal of the
configuration PROM, expensive voltage monitor, brownout detection, and clock generator devices
from the PCB design. Flash-based military ProASIC3/EL devices simplify total system design and
ƒ A3P1000 only supports 1.5 V core operation.
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