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M1A3P1000 View Datasheet(PDF) - Actel Corporation

Part NameDescriptionManufacturer
M1A3P1000 Military ProASIC3/EL Low-Power Flash FPGAs with Flash*Freeze Technology ACTEL
Actel Corporation ACTEL
M1A3P1000 Datasheet PDF : 181 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Military ProASIC3/EL Low-Power Flash FPGAs
I/Os Per Package1
ProASIC3/EL
Low-Power
Devices
ARM
Cortex-M1
Devices
A3PE600L
A3P1000
M1A3P1000
A3PE3000L
M1A3PE3000L
Package
Single-
Ended I/O2
Differential
I/O Pairs
Single-
Ended I/O2
Differential
I/O Pairs
Single-
Ended I/O2
Differential
I/O Pairs
PQ208
154
35
FG144
97
25
FG484
270
135
341
168
FG896
620
300
Notes:
1. When considering migrating your design to a lower- or higher-density device, refer to the packaging section of the
datasheet to ensure you are complying with design and board migration requirements.
2. Each used differential I/O pair reduces the number of single-ended I/Os available by two.
3. "G" indicates RoHS-compliant packages. Refer to "Military ProASIC3/EL Ordering Information" on page iii for the
location of the "G" in the part number.
4. For A3PE3000L devices, the usage of certain I/O standards is limited as follows:
– SSTL3(I) and (II): up to 40 I/Os per north or south bank
– LVPECL / GTL+ 3.3 V / GTL 3.3 V: up to 48 I/Os per north or south bank
– SSTL2(I) and (II) / GTL+ 2.5 V/ GTL 2.5 V: up to 72 I/Os per north or south bank
5. When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not as a regular I/O, the number of single-
ended user I/Os available is reduced by one.
ii
v1.0
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