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M1A3P1000-1FG144M View Datasheet(PDF) - Actel Corporation

Part NameDescriptionManufacturer
M1A3P1000-1FG144M Military ProASIC3/EL Low-Power Flash FPGAs with Flash*Freeze Technology ACTEL
Actel Corporation ACTEL
M1A3P1000-1FG144M Datasheet PDF : 181 Pages
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Military ProASIC3/EL Low-Power Flash FPGAs
PLL Behavior at Brownout Condition
Actel recommends using monotonic power supplies or voltage regulators to ensure proper power-
up behavior. Power ramp-up should be monotonic, at least until VCC and VCCPLX exceed brownout
activation levels. The VCC activation level is specified as 1.1 V worst-case (see Figure 2-2 and
Figure 2-3 on page 2-6 for more details).
When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V
± 0.25 V), the PLL output lock signal goes low and/or the output clock is lost. Refer to the Power-
Up/-Down Behavior of Low-Power Flash Devices chapter of the handbook for information on clock
and lock recovery.
Internal Power-Up Activation Sequence
1. Core
2. Input buffers
Output buffers, after 200 ns delay from input buffer activation.
VCC
VCC = 1.575 V
VCC = 1.425 V
Activation trip point:
Va = 0.85 V ± 0.25 V
Deactivation trip point:
Vd = 0.75 V ± 0.25 V
VCC = VCCI + VT
where VT can be from 0.58 V to 0.9 V (typically 0.75 V)
Region 1: I/O Buffers are OFF
Region 4: I/O
buffers are ON.
I/Os are functional
(except differential inputs)
but slower because VCCI is
below specification. For the
same reason, input buffers do not
meet VIH/VIL levels, and output
buffers do not meet VOH/VOL levels.
Region 5: I/O buffers are ON
and power supplies are within
specification.
I/Os meet the entire datasheet
and timer specifications for
speed,
VIH/VIL
,
V /V
OH OL
,
etc.
Region 2: I/O buffers are ON.
I/Os are functional (except differential inputs)
but slower because VCCI/VCC are below
specification. For the same reason, input
buffers do not meet VIH/VIL levels, and
output buffers do not meet V /V levels.
OH OL
Region 3: I/O buffers are ON.
I/Os are functional; I/O DC
specifications are met,
but I/Os are slower because
the VCC is below specification.
Region 1: I/O buffers are OFF
Activation trip point:
Min VCCI datasheet specification
VCCI
Va = 0.9 V ± 0.3 V
voltage at a selected I/O
Deactivation trip point:
standard; i.e., 1.425 V or 1.7 V
Vd = 0.8 V ± 0.3 V
or 2.3 V or 3.0 V
Figure 2-2 • Devices Operating at 1.5 V Core – I/O State as a Function of VCCI and VCC Voltage Levels
v1.0
2-5
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