AD9211BCPZ-170 View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

AD9211BCPZ-170

10-Bit, 170/200/250 MSPS 1.8 V A/D Converter

Analog Devices 

Preliminary Technical Data

FEATURES

SNR = 60 dBFs @ fIN up to 70 MHz @ 250 MSPS

ENOB of 9.7 @ fIN up to 70 MHz @ 250 MSPS (–0.5 dBFS)

SFDR = 80 dBc@ fIN up to 70 MHz @ 250 MSPS (–0.5 dBFS)

Excellent Linearity

DNL = ±0.3 LSB (Typical)

INL = ±0.5 LSB (Typical)

LVDS at 250 MSPS (ANSI-644 levels)

900 MHz Full Power Analog Bandwidth

On-Chip Reference and Track-and-Hold

Power Dissipation = 380 mW Typical @ 250 MSPS

1.25 V Input Voltage Range

1.8 V Analog Supply Operation

Output Data Format Option

Data Clock Output Provided

Clock Duty Cycle Stabilizer

APPLICATIONS

Wireless and Wired Broadband Communications

Cable Reverse Path

Communications Test Equipment

Radar and Satellite Subsystems

Power Amplifier Linearization

PRODUCT DESCRIPTION

The AD9211 is a 10-Bit monolithic sampling analog-to-digital

converter optimized for high performance, low power, and ease

of use. The product operates up to a 250 MSPS conversion rate

and is optimized for outstanding dynamic performance in

wideband carrier and broadband systems. All necessary

functions, including a track-and-hold (T/H) and voltage

reference, are included on the chip to provide a complete signal

conversion solution.

The ADC requires a 1.8 V analog voltage supply and a

differential clock for full performance operation. The digital

outputs are LVDS (ANSI-644) compatible and support either

twos complement, offset binary format or gray code. A data

clock output is available for proper output data timing.

10-Bit, 170/200/250 MSPS

1.8 V A/D Converter

AD9211

AD9211

Ref

AGND AVDD (1.8V)

DrVDD (1.8V)

VIN+

VIN-

CLK+

CLK-

T/H

ADC 10

10-bit

Core

Output 10

Staging -

LVDS

Clock

Mgmt

Serial Port

RESET SCLK SDIO CSB

DGND

(Pin 0)

D9-D0

(D4-D0 DDR mode)

OTR+

OTR-

DCO+

DCO-

Figure 1. Functional Block Diagram

Fabricated on an advanced CMOS process, the AD9211 is

available in a 56-lead chip scale package (56 LFCSP) specified

over the industrial temperature range (–40°C to +85°C).

PRODUCT HIGHLIGHTS

1. High Performance—Maintains 60 dB SNR @ 250 MSPS

with a 65 MHz input.

2. Low Power—Consumes only 380mW @ 250 MSPS.

3. Ease of Use—LVDS output data and output clock signal

allow interface to current FPGA technology. The on-chip

reference and sample/hold provide flexibility in system

design. Use of a single 1.8 V supply simplifies system

power supply design. Supported DDR mode reduces

number of output data traces

4. Serial Port Control - Standard serial port interface

supports various product functions such as data

formatting, enabling a clock duty cycle stabilizer, power

down, gain adjust and output test pattern generation.

5. Pin compatible family – 12-bit pin compatible family

offered as AD9230.

Rev. PrA

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

Fax: 781.326.8703 © 2006 Analog Devices, Inc. All rights reserved.

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