AD9211-170EB View Datasheet(PDF) - Analog Devices
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AD9211-170EB Datasheet PDF : 21 Pages
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Preliminary Technical Data
HARDWARE INTERFACE
The pins described in Table X comprise the physical interface
between the user’s programming device and the serial port of
the AD9211. All serial pins are inputs, which is an open-drain
output and should be tied to an external pull-up or pull-down
resistor (suggested value 10 kΩ).
This interface is flexible enough to be controlled by either
PROMS or PIC mirocontrollers as well. This provides the user
to use an alternate method to program the ADC other than a
SPI controller.
If the user chooses to not use the SPI interface, some pins serve
a dual function and are associated with a specific function when
strapped externally to AVDD or ground during device power
on. The section below describes the strappable functions
supported on the AD9211. AD9211
CONFIGURATION WITHOUT THE SPI
In applications that do not interface to the SPI control registers,
the SPI SDIO / DCS and SPI SCLK / DFS pins can alternately
serve as stand alone CMOS compatible control pins When the
device is powered up, it is assumed that the user intends to use
the pins as static control lines for the duty cycle stabilizer. In
this mode the SPI CSB chip select should be connected to
AVDD, which will disable the serial port interface.
Table 6. Mode Selection
Pin
External
Voltage
SPI SDIO / DCS AVDD
AGND
SPI SCLK / DFS AVDD
AGND
Configuration
Duty Cycle Stabilizer Enabled
Duty Cycle Stabilizer Disabled
2’s Complement Enabled
Offset Binary Enabled
READING THE MEMORY MAP TABLE
Each row in the memory map table has eight address locations.
The memory map is roughly divided into four sections: chip
AD9211
configuration register map (Address 0x00 to Address 0x02),
device index and transfer register map (Address 0x04 to
Address 0x05, and Address 0xFF), global ADC function register
map (Address 0x08 to Address 0x09), and flexible ADC
functions register map (Address 0x0B to Address 0x25). The
flexible ADC functions register map is product specific.
Starting from the right hand column, the memory map register
in Table X documents the default hex value for each hex address
shown. The column with the heading Byte 7 (MSB) is the start
of the default hex value giving. For example, hex address 0x14,
flex_output_phase has a hex default value of 00h. This means
Bit 3 = 0, Bit 2 = 0, Bit 1 = 1, and Bit 0 = 1 or 0011 in binary.
This setting is the default output clock or DCO phase adjust
option. The default value adjusts the DCO phase 90deg relative
to the Nominal DCO edge and 180deg relative to the data edge.
For more information on this function and others consult the
SPI Doc at www.analog.com.
OPEN LOCATIONS
All locations marked as “open” are currently not supported for
this particular device. When required, these locations should be
written with 0s. Writing to these locations is required only when
part of an address location is open (for example, Address 0x14).
If the whole address location is open (for example, Address
0x13), then this address location does not need to be written.
DEFAULT VALUES
Coming out of reset, some of the address locations (but not all)
are loaded with default values. The default values for the
registers are given in the Table X.
LOGIC LEVELS
An explanation of various registers, “bit is set” is synonymous
with “bit is set to Logic 1” or “writing Logic 1 for the bit.”
Similarly “clear a bit” is synonymous with “bit is set to Logic 0”
or “writing Logic 0 for the bit.”
Figure X. Serial Port Interface Timing Diagram
Rev. PrA | Page 19 of 21
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