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M1A3PE3000-1FGG896YES View Datasheet(PDF) - Microsemi Corporation

Part Name
Description
Manufacturer
M1A3PE3000-1FGG896YES
Microsemi
Microsemi Corporation Microsemi
M1A3PE3000-1FGG896YES Datasheet PDF : 162 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
ProASIC3E Flash Family FPGAs
I/Os Per Package1
ProASIC3E Devices
Cortex-M1 Devices 2
A3PE600
A3PE1500 3
M1A3PE1500
I/O Types
A3PE3000 3
M1A3PE3000
Package
PQ208
147
65
147
65
147
65
FG256
165
79
FG324
221
110
FG484
270
135
280
139
341
168
FG676
444
222
FG896
620
310
Notes:
1. When considering migrating your design to a lower- or higher-density device, refer to the ProASIC3E FPGA Fabric User’s
Guide to ensure compliance with design and board migration requirements.
2. Each used differential I/O pair reduces the number of single-ended I/Os available by two.
3. For A3PE1500 and A3PE3000 devices, the usage of certain I/O standards is limited as follows:
– SSTL3(I) and (II): up to 40 I/Os per north or south bank
– LVPECL / GTL+ 3.3 V / GTL 3.3 V: up to 48 I/Os per north or south bank
– SSTL2(I) and (II) / GTL+ 2.5 V/ GTL 2.5 V: up to 72 I/Os per north or south bank
4. FG256 and FG484 are footprint-compatible packages.
5. When using voltage-referenced I/O standards, one I/O pin should be assigned as a voltage-referenced pin (VREF) per
minibank (group of I/Os).
6. "G" indicates RoHS-compliant packages. Refer to the "ProASIC3E Ordering Information" on page III for the location of the "G"
in the part number.
Table 1-2 • ProASIC3E FPGAs Package Sizes Dimensions
Package
PQ208
FG256
Length × Width (mm\mm)
Nominal Area (mm2)
28 × 28
784
17 × 17
289
Pitch (mm)
0.5
1.0
Height (mm)
3.40
1.60
FG324
19 × 19
361
1.0
1.63
FG484
23 × 23
529
1.0
2.23
FG676
27 × 27
729
1.0
2.23
FG896
31 × 31
961
1.0
2.23
ProASIC3E Device Status
ProASIC3E Devices
A3PE600
A3PE1500
A3PE3000
Status
Production
Production
Production
M1 ProASIC3E Devices
M1A3PE1500
M1A3PE3000
Status
Production
Production
II
Revision 13
 

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