Electronic component search and free download site.
Transistors,MosFET ,Diode,Integrated circuits

ST90E158LV Ver la hoja de datos (PDF) - STMicroelectronics

Número de piezacomponentes DescripciónFabricante
ST90E158LV 8/16-BIT MCU FAMILY WITH UP TO 64K ROM/OTP/EPROM AND UP TO 2K RAM ST-Microelectronics
STMicroelectronics ST-Microelectronics
ST90E158LV Datasheet PDF : 190 Pages
First Prev 11 12 13 14 15 16 17 18 19 20 Next Last
ST90158 - DEVICE ARCHITECTURE
2 DEVICE ARCHITECTURE
2.1 CORE ARCHITECTURE
The ST9+ Core or Central Processing Unit (CPU)
features a highly optimised instruction set, capable
of handling bit, byte (8-bit) and word (16-bit) data,
as well as BCD and Boolean formats; 14 address-
ing modes are available.
Four independent buses are controlled by the
Core: a 16-bit Memory bus, an 8-bit Register data
bus, an 8-bit Register address bus and a 6-bit In-
terrupt/DMA bus which connects the interrupt and
DMA controllers in the on-chip peripherals with the
Core.
This multiple bus architecture affords a high de-
gree of pipelining and parallel operation, thus mak-
ing the ST9+ family devices highly efficient, both
for numerical calculation, data handling and with
regard to communication with on-chip peripheral
resources.
which hold data and control bits for the on-chip
peripherals and I/Os.
– A single linear memory space accommodating
both program and data. All of the physically sep-
arate memory areas, including the internal ROM,
internal RAM and external memory are mapped
in this common address space. The total ad-
dressable memory space of 4 Mbytes (limited by
the size of on-chip memory and the number of
external address pins) is arranged as 64 seg-
ments of 64 Kbytes. Each segment is further
subdivided into four pages of 16 Kbytes, as illus-
trated in Figure 5. A Memory Management Unit
uses a set of pointer registers to address a 22-bit
memory field using 16-bit address-based instruc-
tions.
2.2.1 Register File
2.2 MEMORY SPACES
There are two separate memory spaces:
The Register File consists of (see Figure 6):
– 224 general purpose registers (Group 0 to D,
registers R0 to R223)
– The Register File, which comprises 240 8-bit
registers, arranged as 15 groups (Group 0 to E),
each containing sixteen 8-bit registers plus up to
64 pages of 16 registers mapped in Group F,
– 6 system registers in the System Group (Group
E, registers R224 to R239)
– Up to 64 pages, depending on device configura-
tion, each containing up to 16 registers, mapped
to Group F (R240 to R255), see Figure 7.
Figure 5. Single Program and Data Memory Address Space
up to 4 Mbytes
Address
3FFFFFh
3F0000h
3EFF FFh
3E0000h
Data
16K Pages
255
254
253
252
251
250
249
248
247
Code
64K Segments
63
62
21FFFFh
Reserved
135
134
210000h
133
132
33
20FFFFh
02FFFF h
020000h
01FFFF h
010000h
00FFFF h
000000h
11
10
9
2
8
7
6
5
1
4
3
2
1
0
0
18/190
9
Direct download click here

 

Share Link : 
All Rights Reserved© datasheetq.com 2015 - 2019  ] [ Privacy Policy ] [ Request Datasheet  ] [ Contact Us ]