MT6225 View Datasheet(PDF) - MediaTek Inc

Part Name

Description

Manufacturer

MT6225

GSM/GPRS Baseband Processor

MediaTek Inc 

MT6225 GSM/GPRS Baseband Processor Data Sheet Revision 1.00

value of STR stays “1” regardless of the completion of DMA transfer. Therefore, the software program should be

sure to clear STR to “0” before restarting another DMA transfer.

Note that n is from 1 to 14.

STR

Start control for a DMA channel.

0 The DMA channel is stopped.

1 The DMA channel is started and running.

DMA+0n1Ch DMA Channel n Interrupt Status Register

DMAn_INTSTA

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name

Type

Reset

Bit 15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

Name INT

Type RO

Reset 0

This register shows the interrupt status of a DMA channel. It has the same value as DMA_GLBSTA.

Note that n is from 1 to 14.

INT Interrupt Status for DMA Channel

0 No interrupt request is generated.

1 One interrupt request is pending and waiting for service.

DMA+0n20h DMA Channel n Interrupt Acknowledge Register

Bit 31 30 29 28 27 26 25 24 23 22 21 20

Name

Type

Reset

Bit 15 14 13 12 11 10 9

8

7

6

5

4

Name ACK

Type WO

Reset 0

DMAn_ACKINT

19 18 17 16

3

2

1

0

This register is used to acknowledge the current interrupt request associated with the completion event of a DMA

channel by software program. Note that this is a write-only register, and any read to it returns a value of “0”.

Note that n is from 1 to 14.

ACK

Interrupt acknowledge for the DMA channel

0 No effect

1 Interrupt request is acknowledged and should be relinquished.

DMA+0n24h

DMA Channel n Remaining Length of Current

Transfer

DMAn_RLCT

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name

Type

Reset

Bit 15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

Name

RLCT

Type

RO

Reset

0

This register is to reflect the left amount of the transfer.

Note that n is from 1 to 10.

51

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