MT6225 GSM/GPRS Baseband Processor Data Sheet Revision 1.00
0 Address-wrapping on source .
1 Address-wrapping on destination.
WPEN Address-wrapping for ring buffer. The next address of DMA jumps to WRAP TO address when the current
address matches WRAP POINT count.
NO effect on channel 11 - 14.
0 Disable
1 Enable
DIR Directions of DMA transfer for half-size and Virtual FIFO DMA channels, i.e. channels 4~14. The direction
is from the perspective of the DMA masters. WRITE means read from master and then write to the address
specified in DMA_PGMADDR, and vice versa.
NO effect on channel 1 - 3.
0 Read
1 Write
MAS Master selection. Specifies which master occupies this DMA channel. Once assigned to certain master, the
corresponding DREQ and DACK are connected. For half-size and Virtual FIFO DMA channels, i.e.
channels 4 ~ 14, a predefined address is assigned as well.
00000 SIM
00001 MSDC
00010 IrDA TX
00011 IrDA RX
00100 USB1 Write
00101 USB1 Read
00110 USB2 Write
00111 USB2 Read
01000 UART1 TX
01001 UART1 RX
01010 UART2 TX
01011 UART2 RX
01100 UART3 TX
01101 UART3 RX
01110 DSP-DMA
01111 NFI TX
10000 NFI RX
10001 I2C TX
10010 I2C RX
OTHERS Reserved
DMA+0n18h DMA Channel n Start Register
DMAn_START
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
Bit 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Name STR
Type R/W
Reset 0
This register controls the activity of a DMA channel. Note that prior to setting STR to “1”, all the configurations
should be done by giving proper value to the registers. Note also that once the STR is set to “1”, the hardware does
not clear it automatically no matter if the DMA channel accomplishes the DMA transfer or not. In other works, the
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