DatasheetQ Logo
Electronic component search and free download site.
Transistors,MosFET ,Diode,Integrated circuits

MTV212MV32 View Datasheet(PDF) - Myson Century Inc

Part Name
Description
Manufacturer
MTV212MV32 Datasheet PDF : 27 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
MYSON
TECHNOLOGY
MTV212M32
(Rev 1.1)
OPTION (w) : Chip option configuration (All are "0" in Chip Reset).
PWMF = 1 select 94KHz PWM frequency.
= 0 select 47KHz PWM frequency.
DIV253 = 1 PWM pulse width is 253 step resolution.
= 0 PWM pulse width is 256 step resolution.
FclkE = 1 Double CPU clock freq.
IICpass = 1 HSCL/HSDA pin bypass to ISCL/ISDA pin in DDC2 mode.
= 0 Separate Master and Slave IIC block.
ENSCL = 1 Enable slave IIC block to hold HSCL pin low while MTV212M32 can't catch-up
the external master's speed.
Msel = 1 Master IIC block connect to HSCL/HSDA pins.
= 0 Master IIC block connect to ISCL/ISDA pins.
MIICF1,MIICF0 = 1,1 select 400KHz Master IIC frequency.
= 1,0 select 200KHz Master IIC frequency.
= 0,1 select 50KHz Master IIC frequency.
= 0,0 select 100KHz Master IIC frequency.
SlvAbs1,SlvAbs0 : Slave IIC block A's slave address length.
= 1,0 5-bits slave address.
= 0,1 6-bits slave address.
= 0,0 7-bits slave address.
XBANK (r/w) : Auxiliary RAM bank switch.
Xbnk[2:0]
= 0 Select AUXRAM bank 0.
= 1 Select AUXRAM bank 1.
= 2 Select AUXRAM bank 0.
= 3 Select AUXRAM bank 1.
= 4 Select AUXRAM bank 0.
= 5 Select AUXRAM bank 1.
4. Extra I/O
The extra I/O is a group of I/O pins located in XFR area. Port4 is output mode only. Port5 can be used as
both output and input, because Port5's pin is open drain type, user must write Port5's corresponding bit to
"1" in input mode.
Reg name addr
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
PORT4 38h (w)
P42
P41
P40
PORT5 39h (r/w)
P56
P55
P54
P53
P52
P51
P50
PORT4 (w) : Port 4 data output value.
PORT5 (r/w) : Port 5 data input/output value.
5. PWM DAC
Each PWM DAC converter's output pulse width is controlled by an 8-bit register in XFR. The frequency of
PWM clk is 47KHz or 94KHz, selected by PWMF. And the total duty cycle step of these DAC outputs is 253
or 256, selected by DIV253. If DIV253=1, writing FDH/FEH/FFH to DAC register generates stable high
output. If DIV253=0, the output will pulse low at least once even if the DAC register's content is FFH. Writing
00H to DAC register generates stable low output.
Revision 1.1
- 9-
2000/07/04
 

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]