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M24128-BN6 View Datasheet(PDF) - STMicroelectronics

Part Name
Description
Manufacturer
M24128-BN6 Datasheet PDF : 17 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
M24256, M24128
Table 10. AC Characteristics
M24256 / M24128
Symbol Alt.
Parameter
VCC=4.5 to 5.5 V
TA=–40 to 85°C
VCC=2.5 to 5.5 V
TA=–40 to 85°C
Unit
Min
Max
Min
Max
tCH1CH2
tR Clock Rise Time
300
300
ns
tCL1CL2
tF Clock Fall Time
300
300
ns
tDH1DH2 2
tR SDA Rise Time
20
300
20
300
ns
tDL1DL2 2
tF SDA Fall Time
20
300
20
300
ns
tCHDX 1
tSU:STA Clock High to Input Transition
600
600
ns
tCHCL
tHIGH Clock Pulse Width High
600
600
ns
tDLCL
tHD:STA Input Low to Clock Low (START)
600
600
ns
tCLDX
tHD:DAT Clock Low to Input Transition
0
0
µs
tCLCH
tLOW Clock Pulse Width Low
1.3
1.3
µs
tDXCX
tSU:DAT Input Transition to Clock Transition
100
100
ns
tCHDH
tSU:STO Clock High to Input High (STOP)
600
600
ns
tDHDL
tBUF Input High to Input Low (Bus Free)
1.3
1.3
µs
tCLQV 3
tAA Clock Low to Data Out Valid
200
900
200
900
ns
tCLQX
tDH Data Out Hold Time After Clock Low
200
200
ns
fC
fSCL Clock Frequency
400
400 kHz
tW
tWR Write Time
10
10
ms
Note: 1. For a reSTART condition, or following a write cycle.
2. Sampled only, not 100% tested.
3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
cremented. The master terminates the transfer
with a STOP condition, as shown in Figure 8, with-
out acknowledging the byte output.
Sequential Read
This mode can be initiated with either a Current
Address Read or a Random Address Read. The
master does acknowledge the data byte output in
this case, and the memory continues to output the
next byte in sequence. To terminate the stream of
bytes, the master must not acknowledge the last
byte output, and must generate a STOP condition.
The output data comes from consecutive address-
es, with the internal address counter automatically
incremented after each byte output. After the last
memory address, the address counter ‘rolls-over’
and the memory continues to output data from
memory address 00h.
Acknowledge in Read Mode
In all read modes, the memory waits, after each
byte read, for an acknowledgment during the 9th
bit time. If the master does not pull the SDA line
low during this time, the memory terminates the
data transfer and switches to its stand-by state.
10/17
 

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