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ADDS-21535-EZLITE データシートの表示(PDF) - Analog Devices

部品番号ADDS-21535-EZLITE ADI
Analog Devices ADI
コンポーネント説明1 MSPS 16-/14-Bit Analog I/O Port
ADDS-21535-EZLITE Datasheet PDF : 44 Pages
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AD15700
Table II. Serial Clock Timings in Master Read after Convert
DIVSCLK[1]
DIVSCLK[0]
SYNC to SCLK First Edge Delay Minimum
Internal SCLK Period Minimum
Internal SCLK Period Maximum
Internal SCLK HIGH Minimum
Internal SCLK LOW Minimum
SDOUT Valid Setup Time Minimum
SDOUT Valid Hold Time Minimum
SCLK Last Edge to SYNC Delay Minimum
BUSY HIGH Width Maximum (Warp)
BUSY HIGH Width Maximum (Normal)
BUSY HIGH Width Maximum (Impulse)
0
0
1
1
Symbol 0
1
0
1
Unit
t18
4
20
20
20
ns
t19
25
50
100 200 ns
t19
40
70
140 280 ns
t20
15
25
50
100 ns
t21
9
24
49
99
ns
t22
4.5 22
22
22
ns
t23
2
4
30
89
ns
t24
3
60
140 300 ns
t28
1.5 2
3
5.25 ms
t28
1.75 2.25 3.25 5.5
ms
t28
2
2.5
3.5
5.75 ms
1.6mA IOL
TO OUTPUT
PIN
CL
60pF
500mA IOH
1.4V
IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND
SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD
CL OF 10pF; OTHERWISE THE LOAD IS 60pF MAXIMUM.
Figure 1. Load Circuit for Digital Interface Timing, SDOUT, SYNC, SCLK Outputs, CL = 10 pF
0.8V
2V
tDELAY
2V
0.8V
tDELAY
2V
0.8V
Figure 2. Voltage Reference Levels for Timing
REV. A
–5–
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