|コンポーネント説明||1 MSPS 16-/14-Bit Analog I/O Port|
|ADDS-21535-EZLITE Datasheet PDF : 44 Pages |
The ADC is specified to operate with six full-scale analog input
ranges. Connections required for each of the four analog inputs,
IND, INC, INB, INA, and the resulting full-scale ranges are
shown in Table I. The typical input impedance for each analog
input range is also shown.
Figure 9 shows a simplified analog input section of the ADC.
R = 1.28k⍀
Figure 9. Simplified Analog Input
The four resistors connected to the four analog inputs form a
resistive scaler that scales down and shifts the analog input range
to a common input range of 0 V to 2.5 V at the input of the
switched capacitive ADC.
By connecting the four inputs INA, INB, INC, and IND to the
input signal itself, the ground, or a 2.5 V reference, other analog
input ranges can be obtained.
The diodes shown in Figure 9 provide ESD protection for the
four analog inputs. The inputs INB, INC, and IND, have a high
voltage protection (–11 V to +30 V) to allow wide input voltage
range. Care must be taken to ensure that the analog input signal
never exceeds the absolute ratings on these inputs including
INA (0 V to 5 V). This will cause these diodes to become for-
ward-biased and start conducting current. These diodes can
handle a forward-biased current of 120 mA maximum. For
instance, when using the 0 V to 2.5 V input range, these condi-
tions could eventually occur on the input INA when the input
buffer’s (U1) supplies are different from AVDD. In such case,
an input buffer with a short circuit current limitation can be
used to protect the part.
This analog input structure allows the sampling of the differential
signal between the output of the resistive scaler and INGND.
Unlike other converters, the INGND input is sampled at the same
time as the inputs. By using this differential input, small signals
common to both inputs are rejected as shown in Figure 10, which
represents the typical CMRR over frequency. For instance, by
using INGND to sense a remote signal ground, differences of
ground potentials between the sensor and the local ADC ground
are eliminated. During the acquisition phase for ac signals, the
ADC behaves like a one-pole RC filter consisting of the equivalent
resistance of the resistive scaler R/2 in series with R1 and CS. The
resistor R1 is typically 100 W and is a lumped component made
up of some serial resistor and the on resistance of the switches.
The capacitor CS is typically 60 pF and is mainly the ADC
sampling capacitor. This one-pole filter with a typical –3 dB
cutoff frequency of 9.6 MHz reduces undesirable aliasing effects
and limits the noise coming from the inputs.
FREQUENCY – kHz
Figure 10. Analog Input CMRR vs. Frequency
Except when using the 0 V to 2.5 V analog input voltage range,
the ADC has to be driven by a very low impedance source to
avoid gain errors. That can be done by using the driver amplifier.
When using the 0 V to 2.5 V analog input voltage range, the
input impedance of the ADC is very high so the ADC can be
driven directly by a low impedance source without gain error.
That allows putting an external one-pole RC filter between the
output of the amplifier output and the ADC analog inputs to
even further improve the noise filtering done by the ADC analog
input circuit. However, the source impedance has to be kept low
because it affects the ac performances, especially the total harmonic
distortion (THD). The maximum source impedance depends on
the amount of total THD that can be tolerated. The THD degra-
dation is a function of the source impedance and the maximum
input frequency, as shown in Figure 11.
R = 100⍀
R = 50⍀
R = 11⍀
FREQUENCY – kHz
Figure 11. THD vs. Analog Input Frequency and
Input Resistance (0 V to 2.5 V Only)
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