|コンポーネント説明||1 MSPS 16-/14-Bit Analog I/O Port|
|ADDS-21535-EZLITE Datasheet PDF : 44 Pages |
Analog Input Section
Made up of a buffer amplifier, an RC filter, and an ADC, the
analog input circuit allows measurement of voltages ranging from
0.2 V to 2 REF V. When placed in the 0 V to REF input range,
the circuit has the configuration shown in Figure 5a.
Figure 5a. Analog Input Circuit
The filter is made up of one of the AD15700’s internal center-
tapped resistors, an external capacitor C2, plus the ADC’s internal
resistance and capacitance. The transfer function of this filter is
( ) H
8.11425 ¥ 106
202.288 s2C 2 + s +
With C2 set to 100 pF, the bandwidth is 1.2 MHz. Without C2,
the bandwidth of the filter is 2.6 MHz. To utilize the ADC’s
maximum 9.6 MHz bandwidth, the components external to the
ADC are eliminated. In this case, the ADC is configured for its
0 to 2 REF input range and the resulting equivalent input circuit
is shown in Figure 5b.
Figure 5b. Analog Input Circuit
Analog Output Section
The output circuitry consists of a DAC, RC filter, and an amplifier.
The circuit uses the DAC’s output resistance of 6.25 kW ± 20%
to form a single-pole RC filter with an external capacitor C1. One
of the AD15700’s internal center-tapped resistors and one of its
op amps form an amplifier with a gain of two. The gain is used to
bring the DAC’s maximum range of REF volts up to 2 REF V.
Figure 6. Analog Output Circuit
Voltage Reference Input
The AD15700 uses an external 2.5 V or 3.0 V voltage reference.
Because of the dynamic input impedance of the A/D and the
code dependent impedance of the D/A, the reference inputs must
be driven by a low impedance source. Decoupling consisting of a
parallel combination of 47 mF and 0.1 mF capacitors is recom-
mended. Suitable references include the ADR421 for 2.5 V output
and the AD780 for selectable 2.5 V or 3.0 V output. Both of these
feature low noise and low temperature drift.
The circuit in Figure 5a uses serial interfacing to minimize the
number of signals that connect to the digital circuits. External
logic such as a state machine is used to generate clocks and other
timing signals for the interface. Ideally, the clocks supplied to the
converters are discontinuous and operate at the maximum frequency
supported by the converter and the processor. Discontinuous
clocks that are quiet during critical times minimize degradation
caused by voltage transients on the digital interface. It is best to
keep the clocks quiet during ADC conversion and when the DAC
output is sampled by the external system. Often, the processor
cannot tolerate a discontinuous clock and therefore a separate
continuous clock (or clocks) that is synchronous with the converter
clocks must be generated. Separate clocks for the DAC and ADC
are used to maximize the data transfer rate to each converter.
The ADC operates at a maximum rate of 40 MHz while the DAC
can operate up to 25 MHz.
ADC CIRCUIT INFORMATION
The ADC is a fast, low power, single-supply precise 16-bit analog-
to-digital converter (ADC). It features different modes to optimize
performances according to the applications.
In warp mode, it is capable of converting 1,000,000 samples per
second (1 MSPS).
The ADC provides the user with an on-chip track/hold, successive
approximation ADC that does not exhibit any pipeline or latency,
making it ideal for multiple multiplexed channel applications.
It is specified to operate with both bipolar and unipolar input
ranges by changing the connection of its input resistive scaler.
The ADC can be operated from a single 5 V supply and be inter-
faced to either 5 V or 3 V digital logic.
ADC CONVERTER OPERATION
The ADC is a successive approximation analog-to-digital con-
verter based on a charge redistribution DAC. Figure 7 shows the
simplified schematic of the ADC. The input analog signal is first
scaled down and level-shifted by the internal input resistive scaler,
which allows both unipolar ranges (0 V to 2.5 V, 0 V to 5 V, and
0 to 10 V) and bipolar ranges (± 2.5 V, ± 5 V, and ± 10 V). The
output voltage range of the resistive scaler is always 0 V to 2.5 V.
The capacitive DAC consists of an array of 16 binary weighted
capacitors and an additional LSB capacitor. The comparator’s
negative input is connected to a “dummy” capacitor of the same
value as the capacitive DAC array.
During the acquisition phase, the common terminal of the array
tied to the comparator’s positive input is connected to AGND
via SWA. All independent switches are connected to the output
of the resistive scaler. Thus, the capacitor array is used as a
sampling capacitor and acquires the analog signal. Similarly, the
dummy capacitor acquires the analog signal on INGND input.
When the acquisition phase is complete, and the CNVST input
goes or is low, a conversion phase is initiated. When the conversion
phase begins, SWA and SWB are opened first. The capacitor
array and the dummy capacitor are then disconnected from the
inputs and connected to the REFGND input. Therefore, the differ-
ential voltage between the output of the resistive scaler and INGND
captured at the end of the acquisition phase is applied to the
comparator inputs, causing the comparator to become unbalanced.
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